mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-09 09:21:58 +00:00
chtype: replace publish pass with chtype -publish_icells
This commit is contained in:
parent
4706c82c31
commit
72c2081e29
3 changed files with 32 additions and 44 deletions
|
@ -57,4 +57,3 @@ OBJS += passes/cmds/abstract.o
|
|||
OBJS += passes/cmds/test_select.o
|
||||
OBJS += passes/cmds/timeest.o
|
||||
OBJS += passes/cmds/linecoverage.o
|
||||
OBJS += passes/cmds/publish.o
|
||||
|
|
|
@ -22,6 +22,27 @@
|
|||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
static void publish(RTLIL::IdString& id) {
|
||||
if (id.begins_with("$")) {
|
||||
log_debug("publishing %s\n", id.c_str());
|
||||
id = "\\" + id.str();
|
||||
log_debug("published %s\n", id.c_str());
|
||||
}
|
||||
}
|
||||
|
||||
static void publish_design(RTLIL::Design* design) {
|
||||
auto saved_modules = design->modules_;
|
||||
design->modules_.clear();
|
||||
for (auto& [name, mod] : saved_modules) {
|
||||
publish(mod->name);
|
||||
design->modules_[mod->name] = mod;
|
||||
for (auto* cell : mod->cells()) {
|
||||
publish(cell->type);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
struct ChtypePass : public Pass {
|
||||
ChtypePass() : Pass("chtype", "change type of cells in the design") { }
|
||||
void help() override
|
||||
|
@ -38,12 +59,16 @@ struct ChtypePass : public Pass {
|
|||
log(" -map <old_type> <new_type>\n");
|
||||
log(" change cells types that match <old_type> to <new_type>\n");
|
||||
log("\n");
|
||||
log(" -publish_icells\n");
|
||||
log(" change internal cells types to public types\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
IdString set_type;
|
||||
dict<IdString, IdString> map_types;
|
||||
bool publish_mode = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
|
@ -58,10 +83,17 @@ struct ChtypePass : public Pass {
|
|||
map_types[old_type] = new_type;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-publish_icells") {
|
||||
publish_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (publish_mode)
|
||||
publish_design(design);
|
||||
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
for (auto cell : module->selected_cells())
|
||||
|
|
|
@ -1,43 +0,0 @@
|
|||
#include "kernel/register.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct PublishPass : public Pass {
|
||||
private:
|
||||
static void publish(RTLIL::IdString& id) {
|
||||
if (id.begins_with("$")) {
|
||||
log_debug("publishing %s\n", id.c_str());
|
||||
id = "\\" + id.str();
|
||||
log_debug("published %s\n", id.c_str());
|
||||
}
|
||||
}
|
||||
public:
|
||||
PublishPass() : Pass("publish", "publish private cell types") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" publish\n");
|
||||
log("Makes all module names and cell types public by prefixing\n");
|
||||
log("%% with \\.\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing PUBLISH pass. (make cell types public)\n");
|
||||
extra_args(args, 1, design);
|
||||
auto saved_modules = design->modules_;
|
||||
design->modules_.clear();
|
||||
for (auto& [name, mod] : saved_modules) {
|
||||
publish(mod->name);
|
||||
design->modules_[mod->name] = mod;
|
||||
for (auto* cell : mod->cells()) {
|
||||
publish(cell->type);
|
||||
}
|
||||
}
|
||||
}
|
||||
} PublishPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
Loading…
Add table
Add a link
Reference in a new issue