mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 03:16:22 +00:00
Code Activity

signorm: safer indexing if broken invariant

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-05-22 17:21:40 +02:00
parent dcc68e49fb
commit 72b60b6cef
1 changed files with 28 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

52
kernel/rtlil_bufnorm.cc
View file

@ -149,9 +149,11 @@ struct RTLIL::SigNormIndex
if (cell->port_dir(port) != RTLIL::PD_INPUT) if (cell->port_dir(port) != RTLIL::PD_INPUT)
continue; continue;
int i = 0; int i = 0;
for (auto bit : sig) for (auto bit : sig) {
if (bit.is_wire()) if (bit.is_wire())
fanout[bit].insert(PortBit(cell, port, i++)); fanout[bit].insert(PortBit(cell, port, i));
i++;
}
} }
} }
} }
@ -995,17 +997,17 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
bool is_input_port = port_dir(portname) == RTLIL::PD_INPUT; bool is_input_port = port_dir(portname) == RTLIL::PD_INPUT;
if (is_input_port) { if (is_input_port) {
auto &fanout = module->sig_norm_index->fanout; auto &fanout = module->sig_norm_index->fanout;
int counter = 0; int i = 0;
for (auto bit : conn_it->second) { for (auto bit : conn_it->second) {
if (!bit.is_wire()) if (bit.is_wire()) {
continue; auto found = fanout.find(bit);
int i = counter++; log_assert(found != fanout.end());
auto found = fanout.find(bit); int erased = found->second.erase(PortBit(this, portname, i));
log_assert(found != fanout.end()); log_assert(erased);
int erased = found->second.erase(PortBit(this, portname, i)); if (found->second.empty())
log_assert(erased); fanout.erase(found);
if (found->second.empty()) }
fanout.erase(found); i++;
} }
} else if (GetSize(conn_it->second)) { } else if (GetSize(conn_it->second)) {
Wire *w = conn_it->second.as_wire(); Wire *w = conn_it->second.as_wire();
@ -1129,17 +1131,17 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
if (!r.second) { if (!r.second) {
if (is_input_port) { if (is_input_port) {
auto &fanout = module->sig_norm_index->fanout; auto &fanout = module->sig_norm_index->fanout;
int counter = 0; int i = 0;
for (auto bit : conn_it->second) { for (auto bit : conn_it->second) {
if (!bit.is_wire()) if (bit.is_wire()) {
continue; auto found = fanout.find(bit);
int i = counter++; log_assert(found != fanout.end());
auto found = fanout.find(bit); int erased = found->second.erase(PortBit(this, portname, i));
log_assert(found != fanout.end()); log_assert(erased);
int erased = found->second.erase(PortBit(this, portname, i)); if (found->second.empty())
log_assert(erased); fanout.erase(found);
if (found->second.empty()) }
fanout.erase(found); i++;
} }
} else { } else {
Wire *w = conn_it->second.as_wire(); Wire *w = conn_it->second.as_wire();
@ -1153,9 +1155,11 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
if (is_input_port) { if (is_input_port) {
auto &fanout = module->sig_norm_index->fanout; auto &fanout = module->sig_norm_index->fanout;
int i = 0; int i = 0;
for (auto bit : signal) for (auto bit : signal) {
if (bit.is_wire()) if (bit.is_wire())
fanout[bit].insert(PortBit(this, portname, i++)); fanout[bit].insert(PortBit(this, portname, i));
i++;
}
} else if (GetSize(signal)) { } else if (GetSize(signal)) {
Wire *w = signal.as_wire(); Wire *w = signal.as_wire();
log_assert(w->driverCell_ == nullptr); log_assert(w->driverCell_ == nullptr);