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Merge pull request #2632 from zachjs/width-limit

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verilog: impose limit on maximum expression width
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whitequark 2021-03-07 03:45:41 -08:00 • committed by GitHub
commit 72ae15c77c
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17
tests/verilog/absurd_width.ys Normal file
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@ -0,0 +1,17 @@
logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
read_verilog <<EOF
module top(
input inp,
output out
);
assign out =
{1024 {
{1024 {
{1024 {
inp
}}
}}
}}
;
endmodule
EOF

16
tests/verilog/absurd_width_const.ys Normal file
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@ -0,0 +1,16 @@
logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
read_verilog <<EOF
module top(
output out
);
assign out =
{1024 {
{1024 {
{1024 {
1'b1
}}
}}
}}
;
endmodule
EOF