mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Merge pull request #2632 from zachjs/width-limit

Browse source 
verilog: impose limit on maximum expression width
This commit is contained in:
whitequark 2021-03-07 03:45:41 -08:00 • committed by GitHub
commit 72ae15c77c
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 39 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
frontends/ast/genrtlil.cc
View file

@ -1000,6 +1000,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
if (found_real)
*found_real = false;
detectSignWidthWorker(width_hint, sign_hint, found_real);
constexpr int kWidthLimit = 1 << 24;
if (width_hint >= kWidthLimit)
log_file_error(filename, location.first_line,
"Expression width %d exceeds implementation limit of %d!\n",
width_hint, kWidthLimit);
}
static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,