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Merge pull request #2632 from zachjs/width-limit

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verilog: impose limit on maximum expression width
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whitequark 2021-03-07 03:45:41 -08:00 • committed by GitHub
commit 72ae15c77c
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6
frontends/ast/genrtlil.cc
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@ -1000,6 +1000,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
if (found_real)
*found_real = false;
detectSignWidthWorker(width_hint, sign_hint, found_real);
constexpr int kWidthLimit = 1 << 24;
if (width_hint >= kWidthLimit)
log_file_error(filename, location.first_line,
"Expression width %d exceeds implementation limit of %d!\n",
width_hint, kWidthLimit);
}
static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,