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fixup! WIP add placeholder $connect cell

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This commit is contained in:
Jannis Harder 2025-08-14 16:15:28 +02:00
parent b394629e3f
commit 727dabba95
2 changed files with 16 additions and 0 deletions
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15
kernel/rtlil.cc
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@ -5477,6 +5477,21 @@ bool RTLIL::SigSpec::has_const() const
return false;
}
bool RTLIL::SigSpec::has_const(RTLIL::State state) const
{
cover("kernel.rtlil.sigspec.has_const");
pack();
for (auto it = chunks_.begin(); it != chunks_.end(); it++)
if (it->width > 0 && it->wire == NULL) {
for (size_t i = 0; i < it->data.size(); i++)
if (it->data[i] == state)
return true;
}
return false;
}
bool RTLIL::SigSpec::has_marked_bits() const
{
cover("kernel.rtlil.sigspec.has_marked_bits");