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Added basic support for $expect cells

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This commit is contained in:
Clifford Wolf 2016-07-13 16:56:17 +02:00
parent b3155af5f6
commit 721f1f5ecf
16 changed files with 82 additions and 19 deletions
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1
frontends/verilog/verilog_lexer.l
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@ -173,6 +173,7 @@ YOSYS_NAMESPACE_END
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"expect" { if (formal_mode) return TOK_EXPECT; SV_KEYWORD(TOK_EXPECT); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }

9
frontends/verilog/verilog_parser.y
View file

@ -112,7 +112,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME TOK_PROPERTY
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
%token TOK_EXPECT TOK_PROPERTY
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@ -965,6 +966,9 @@ assert:
} |
TOK_ASSUME '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
} |
TOK_EXPECT '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $3));
};
assert_property:
@ -973,6 +977,9 @@ assert_property:
} |
TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
} |
TOK_EXPECT TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $4));
};
simple_behavioral_stmt: