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https://github.com/YosysHQ/yosys
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Added basic support for $expect cells
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parent
b3155af5f6
commit
721f1f5ecf
16 changed files with 82 additions and 19 deletions
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@ -82,6 +82,7 @@ std::string AST::type2str(AstNodeType type)
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X(AST_PREFIX)
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X(AST_ASSERT)
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X(AST_ASSUME)
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X(AST_EXPECT)
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X(AST_FCALL)
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X(AST_TO_BITS)
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X(AST_TO_SIGNED)
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@ -65,6 +65,7 @@ namespace AST
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AST_PREFIX,
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AST_ASSERT,
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AST_ASSUME,
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AST_EXPECT,
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AST_FCALL,
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AST_TO_BITS,
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@ -1296,7 +1296,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// generate $assert cells
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case AST_ASSERT:
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case AST_ASSUME:
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case AST_EXPECT:
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{
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const char *celltype = "$assert";
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if (type == AST_ASSUME) celltype = "$assume";
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if (type == AST_EXPECT) celltype = "$expect";
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log_assert(children.size() == 2);
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RTLIL::SigSpec check = children[0]->genRTLIL();
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@ -1308,9 +1313,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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en = current_module->ReduceBool(NEW_ID, en);
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std::stringstream sstr;
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sstr << (type == AST_ASSERT ? "$assert$" : "$assume$") << filename << ":" << linenum << "$" << (autoidx++);
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sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_ASSERT ? "$assert" : "$assume");
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
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cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
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for (auto &attr : attributes) {
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@ -1348,10 +1348,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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}
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skip_dynamic_range_lvalue_expansion:;
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if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && current_block != NULL)
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if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && current_block != NULL)
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{
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std::stringstream sstr;
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sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
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sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
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std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN";
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AstNode *wire_check = new AstNode(AST_WIRE);
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@ -1363,8 +1363,10 @@ skip_dynamic_range_lvalue_expansion:;
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AstNode *wire_en = new AstNode(AST_WIRE);
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wire_en->str = id_en;
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current_ast_mod->children.push_back(wire_en);
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current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)))));
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current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en;
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if (current_always == nullptr || current_always->type != AST_INITIAL) {
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current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)))));
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current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en;
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}
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current_scope[wire_en->str] = wire_en;
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while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
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@ -1403,7 +1405,7 @@ skip_dynamic_range_lvalue_expansion:;
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goto apply_newNode;
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}
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if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && children.size() == 1)
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if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && children.size() == 1)
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{
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children.push_back(mkconst_int(1, false, 1));
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did_something = true;
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