Add test_cell tests for C++ functional backend

tests/functional/single_cells/rtlil/test_cell_add_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $add \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_alu_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 7 input 2 \B
+  wire input 3 \BI
+  wire input 4 \CI
+  wire width 6 output 5 \CO
+  wire width 6 output 6 \X
+  wire width 6 output 7 \Y
+  cell $alu \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \BI \BI
+    connect \CI \CI
+    connect \CO \CO
+    connect \X \X
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_and_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 3 input 2 \B
+  wire width 2 output 3 \Y
+  cell $and \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_bmux_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire input 2 \S
+  wire width 4 output 3 \Y
+  cell $bmux \UUT
+    parameter \S_WIDTH 1
+    parameter \WIDTH 4
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_demux_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 5 input 2 \S
+  wire width 192 output 3 \Y
+  cell $demux \UUT
+    parameter \S_WIDTH 5
+    parameter \WIDTH 6
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_div_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 6 input 2 \B
+  wire output 3 \Y
+  cell $div \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $divfloor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_eq_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire input 2 \B
+  wire width 4 output 3 \Y
+  cell $eq \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_fa_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \C
+  wire output 4 \X
+  wire output 5 \Y
+  cell $fa \UUT
+    parameter \WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \C \C
+    connect \X \X
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_ge_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 7 input 2 \B
+  wire width 6 output 3 \Y
+  cell $ge \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_gt_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 3 input 2 \B
+  wire width 4 output 3 \Y
+  cell $gt \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_lcu_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \CI
+  wire width 2 output 2 \CO
+  wire width 2 input 3 \G
+  wire width 2 input 4 \P
+  cell $lcu \UUT
+    parameter \WIDTH 2
+    connect \CI \CI
+    connect \CO \CO
+    connect \G \G
+    connect \P \P
+  end
+end

tests/functional/single_cells/rtlil/test_cell_le_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $le \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 7 input 2 \B
+  wire output 3 \Y
+  cell $logic_and \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 8 output 2 \Y
+  cell $logic_not \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 7 input 2 \B
+  wire width 2 output 3 \Y
+  cell $logic_or \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_lt_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 5 input 2 \B
+  wire width 6 output 3 \Y
+  cell $lt \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_lut_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire output 2 \Y
+  cell $lut \UUT
+    parameter \LUT 4'1111
+    parameter \WIDTH 2
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_macc_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 0 input 2 \B
+  wire width 2 output 3 \Y
+  cell $macc \UUT
+    parameter \A_WIDTH 3
+    parameter \B_WIDTH 0
+    parameter \CONFIG 10'0110000010
+    parameter \CONFIG_WIDTH 10
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B { }
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_mod_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 8 input 2 \B
+  wire width 2 output 3 \Y
+  cell $mod \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 7 input 2 \B
+  wire width 4 output 3 \Y
+  cell $modfloor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_mul_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 2 input 2 \B
+  wire width 5 output 3 \Y
+  cell $mul \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_mux_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 input 2 \B
+  wire input 3 \S
+  wire width 4 output 4 \Y
+  cell $mux \UUT
+    parameter \WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_ne_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 5 input 2 \B
+  wire width 4 output 3 \Y
+  cell $ne \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_neg_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 5 output 2 \Y
+  cell $neg \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_not_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 7 output 2 \Y
+  cell $not \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_or_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire input 2 \B
+  wire width 2 output 3 \Y
+  cell $or \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_pos_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 3 output 2 \Y
+  cell $pos \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 5 output 2 \Y
+  cell $reduce_and \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 2 output 2 \Y
+  cell $reduce_bool \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 7 output 2 \Y
+  cell $reduce_or \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 output 2 \Y
+  cell $reduce_xnor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire output 2 \Y
+  cell $reduce_xor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shift_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 6 input 2 \B
+  wire width 4 output 3 \Y
+  cell $shift \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 5 input 2 \B
+  wire width 3 output 3 \Y
+  cell $shiftx \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shl_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 2 input 2 \B
+  wire width 3 output 3 \Y
+  cell $shl \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shr_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 6 input 2 \B
+  wire width 4 output 3 \Y
+  cell $shr \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sop_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire output 2 \Y
+  cell $sop \UUT
+    parameter \DEPTH 8
+    parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110
+    parameter \WIDTH 8
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sshl_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 3 input 2 \B
+  wire width 6 output 3 \Y
+  cell $sshl \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sshr_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 2 input 2 \B
+  wire width 2 output 3 \Y
+  cell $sshr \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sub_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 6 input 2 \B
+  wire width 6 output 3 \Y
+  cell $sub \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_xnor_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 8 input 2 \B
+  wire width 7 output 3 \Y
+  cell $xnor \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_xor_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 2 input 2 \B
+  wire width 8 output 3 \Y
+  cell $xor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 8
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end