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Add bitwise $bweqx and $bwmux cells

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The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
This commit is contained in:
Jannis Harder 2022-11-02 17:12:51 +01:00
parent f2c531e65f
commit 7203ba7bc1
9 changed files with 179 additions and 11 deletions
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23
kernel/calc.cc
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@ -690,5 +690,28 @@ RTLIL::Const RTLIL::const_demux(const RTLIL::Const &arg1, const RTLIL::Const &ar
return res;
}
RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2)
{
log_assert(arg2.size() == arg1.size());
RTLIL::Const result(RTLIL::State::S0, arg1.size());
for (int i = 0; i < arg1.size(); i++)
result[i] = arg1[i] == arg2[i] ? State::S1 : State::S0;
return result;
}
RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3)
{
log_assert(arg2.size() == arg1.size());
log_assert(arg3.size() == arg1.size());
RTLIL::Const result(RTLIL::State::Sx, arg1.size());
for (int i = 0; i < arg1.size(); i++) {
if (arg3[i] != State::Sx || arg1[i] == arg2[i])
result[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i];
}
return result;
}
YOSYS_NAMESPACE_END