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ast, flatten, hierarchy: canonically split hierarchical references into twines

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This commit is contained in:
Emil J. Tywoniak 2026-06-23 10:53:35 +02:00
parent ba4ea22831
commit 71e6e31795
5 changed files with 38 additions and 24 deletions
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16
frontends/ast/ast.cc
View file

@ -1104,6 +1104,22 @@ std::string AstNode::loc_string() const
return stringf("%s:%d.%d-%d.%d", location.begin.filename->c_str(), location.begin.line, location.begin.column, location.end.line, location.end.column);
}
static TwineRef build_hier_content(TwinePool &pool, std::string_view content)
{
size_t dot = content.rfind('.');
if (dot == std::string_view::npos)
return pool.add(Twine{std::string{content}}).tag(true);
TwineRef prefix = build_hier_content(pool, content.substr(0, dot));
return pool.add(Twine{Twine::Suffix{prefix, std::string{content.substr(dot)}}});
}
TwineRef AST::intern_hier_name(RTLIL::Design *design, std::string_view escaped)
{
if (escaped.size() > 1 && escaped[0] == '\\')
return build_hier_content(design->twines, escaped.substr(1));
return design->twines.add(std::string{escaped});
}
void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
{
if (!current_module || !current_module->design)

3
frontends/ast/ast.h
View file

@ -429,6 +429,9 @@ namespace AST
AstNode * find_modport(AstNode *intf, std::string name);
void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);
// Intern Verilog hierarchical reference "a.b.c" as a Suffix chain "a" ".b" ".c"
TwineRef intern_hier_name(RTLIL::Design *design, std::string_view escaped);
// Helper for setting the src attribute.
void set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);

16
frontends/ast/genrtlil.cc
View file

@ -178,7 +178,7 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
to_add_kind, id.c_str(), existing_kind, location_str.c_str());
};
TwineRef id_tw = module->design->twines.find(id.str());
TwineRef id_tw = intern_hier_name(module->design, id.str());
if (const RTLIL::Wire *wire = module->wire(id_tw))
already_exists(wire, "signal");
if (const RTLIL::Cell *cell = module->cell(id_tw))
@ -1478,7 +1478,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// signals.
RTLIL::IdString id = str;
check_unique_id(current_module, id, this, "interface port");
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{id.str()}), 1);
RTLIL::Wire *wire = current_module->addWire(intern_hier_name(current_module->design, id.str()), 1);
set_src_attr(wire, this);
wire->start_offset = 0;
wire->port_id = port_id;
@ -1518,7 +1518,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::Const val = children[0]->bitsAsConst();
RTLIL::IdString id = str;
check_unique_id(current_module, id, this, "pwire");
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{id.str()}), GetSize(val));
RTLIL::Wire *wire = current_module->addWire(intern_hier_name(current_module->design, id.str()), GetSize(val));
current_module->connect(wire, val);
wire->is_signed = children[0]->is_signed;
@ -1543,7 +1543,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::IdString id = str;
check_unique_id(current_module, id, this, "signal");
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{id.str()}), range_left - range_right + 1);
RTLIL::Wire *wire = current_module->addWire(intern_hier_name(current_module->design, id.str()), range_left - range_right + 1);
set_src_attr(wire, this);
wire->start_offset = range_right;
wire->port_id = port_id;
@ -1574,7 +1574,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
input_error("Memory `%s' with non-constant width or size!\n", str);
check_unique_id(current_module, RTLIL::IdString(str), this, "memory");
RTLIL::Memory *memory = current_module->addMemory(current_module->design->twines.add(std::string{str}));
RTLIL::Memory *memory = current_module->addMemory(intern_hier_name(current_module->design, str));
set_src_attr(memory, this);
memory->width = children[0]->range_left - children[0]->range_right + 1;
if (children[1]->range_right < children[1]->range_left) {
@ -1629,10 +1629,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_assert(id2ast != nullptr);
TwineRef str_ref = current_module->design->twines.find(str);
TwineRef str_ref = intern_hier_name(current_module->design, str);
if (id2ast->type == AST_AUTOWIRE && current_module->wire(str_ref) == nullptr) {
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{str}));
RTLIL::Wire *wire = current_module->addWire(str_ref);
str_ref = wire->name.ref();
set_src_attr(wire, this);
@ -2192,7 +2192,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::IdString id = str;
check_unique_id(current_module, id, this, "cell");
RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{id.str()}), Twine::Null);
RTLIL::Cell *cell = current_module->addCell(intern_hier_name(current_module->design, id.str()), Twine::Null);
set_src_attr(cell, this);
for (auto it = children.begin(); it != children.end(); it++) {