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Fix tests; Remove simulation;

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- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
This commit is contained in:
SergeyDegtyar 2019-08-20 15:52:25 +03:00
parent 153ec0541c
commit 71dd412ac5
26 changed files with 33 additions and 519 deletions
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19
tests/ice40/run-test.sh
View file

@ -1,21 +1,6 @@
#!/bin/bash
set -e
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
TECHLIBS_PREFIX=../../../../../techlibs
else
COMMON_PREFIX=/usr/local/share/yosys
TECHLIBS_PREFIX=/usr/local/share/yosys
fi
for x in *_top.v; do
for x in *.v; do
echo "Running $x.."
../../yosys -q -s ${x%_top.v}.ys -l ./temp/${x%.v}.log $x
echo "Simulating $x.."
iverilog -o ./temp/${x%_top.v}_testbench ${x%_top.v}_tb.v ./temp/${x%_top.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
if ! vvp -N ./temp/${x%_top.v}_testbench > ./temp/${x%_top.v}_testbench.log 2>&1; then
grep 'ERROR' ./temp/${x%_top.v}_testbench.log
exit 0
elif grep 'ERROR' ./temp/${x%_top.v}_testbench.log || ! grep 'OKAY' ./temp/${x%_top.v}_testbench.log; then
exit 0
fi
../../yosys -q -s ${x%.v}.ys -l ./temp/${x%.v}.log $x
done