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Fix tests; Remove simulation;

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- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
This commit is contained in:
SergeyDegtyar 2019-08-20 15:52:25 +03:00
parent 153ec0541c
commit 71dd412ac5
26 changed files with 33 additions and 519 deletions
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9
tests/ice40/div_mod.ys
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@ -1,5 +1,6 @@
synth_ice40
equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40
select -assert-count 89 t:SB_LUT4
select -assert-count 66 t:SB_CARRY
write_verilog ./temp/div_mod_synth.v
#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
equiv_opt -map +/ice40/cells_sim.v synth_ice40
design -load postopt
select -assert-count 85 t:SB_LUT4
select -assert-count 54 t:SB_CARRY