mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-12 22:20:55 +00:00
Code Activity

Fix tests; Remove simulation;

Browse source 
- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
This commit is contained in:
SergeyDegtyar 2019-08-20 15:52:25 +03:00
parent 153ec0541c
commit 71dd412ac5
26 changed files with 33 additions and 519 deletions
Download patch file Download diff file Expand all files Collapse all files

11
tests/ice40/dffs.ys
View file

@ -1,5 +1,12 @@
equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40
proc
flatten
dff2dffe
synth_ice40
#equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40
equiv_opt -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40
design -load postopt
select -assert-count 2 t:SB_DFFR
select -assert-count 1 t:SB_DFFE
write_verilog ./temp/dffs_synth.v
select -assert-count 4 t:SB_LUT4
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:$_DFFSR_NPP_