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Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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parent
634482380c
commit
71c38d9de5
9 changed files with 133 additions and 6 deletions
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@ -952,7 +952,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM)
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continue;
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if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
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(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3"))
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(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule"))
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continue;
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blackbox_module = false;
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break;
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@ -1039,7 +1039,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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child->children.push_back(AstNode::mkconst_int(0, false, 0));
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new_children.push_back(child);
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} else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
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(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3")) {
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(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) {
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new_children.push_back(child);
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} else {
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delete child;
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@ -1538,6 +1538,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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cell->setParam("\\SRC_WIDTH", Const(src_width));
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cell->setParam("\\DST_WIDTH", Const(dst_width));
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}
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if (cell->type == "$specrule") {
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int src_width = GetSize(cell->getPort("\\SRC"));
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int dst_width = GetSize(cell->getPort("\\DST"));
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cell->setParam("\\SRC_WIDTH", Const(src_width));
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cell->setParam("\\DST_WIDTH", Const(dst_width));
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}
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}
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break;
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