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Use C++11 final/override keywords.

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This commit is contained in:
whitequark 2020-06-18 23:34:52 +00:00
parent dfde1cf1c5
commit 7191dd16f9
220 changed files with 540 additions and 548 deletions
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8
techlibs/achronix/synth_achronix.cc
View file

@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthAchronixPass : public ScriptPass {
SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -63,7 +63,7 @@ struct SynthAchronixPass : public ScriptPass {
string top_opt, family_opt, vout_file;
bool retime, flatten;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
vout_file = "";
@ -71,7 +71,7 @@ struct SynthAchronixPass : public ScriptPass {
flatten = true;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -118,7 +118,7 @@ struct SynthAchronixPass : public ScriptPass {
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

4
techlibs/anlogic/anlogic_eqn.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct AnlogicEqnPass : public Pass {
AnlogicEqnPass() : Pass("anlogic_eqn", "Anlogic: Calculate equations for luts") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" anlogic_eqn [selection]\n");
@ -63,7 +63,7 @@ struct AnlogicEqnPass : public Pass {
return Const(eqn);
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ANLOGIC_EQN pass (calculate equations for luts).\n");

4
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -98,7 +98,7 @@ static void fix_carry_chain(Module *module)
struct AnlogicCarryFixPass : public Pass {
AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -107,7 +107,7 @@ struct AnlogicCarryFixPass : public Pass {
log("Add Anlogic adders to fix carry chain if needed.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");

8
techlibs/anlogic/synth_anlogic.cc
View file

@ -30,7 +30,7 @@ struct SynthAnlogicPass : public ScriptPass
{
SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -72,7 +72,7 @@ struct SynthAnlogicPass : public ScriptPass
string top_opt, edif_file, json_file;
bool flatten, retime, nolutram;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
edif_file = "";
@ -82,7 +82,7 @@ struct SynthAnlogicPass : public ScriptPass
nolutram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -137,7 +137,7 @@ struct SynthAnlogicPass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

8
techlibs/common/prep.cc
View file

@ -29,7 +29,7 @@ struct PrepPass : public ScriptPass
{
PrepPass() : ScriptPass("prep", "generic synthesis script") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -81,7 +81,7 @@ struct PrepPass : public ScriptPass
string top_module, fsm_opts;
bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_module.clear();
@ -94,7 +94,7 @@ struct PrepPass : public ScriptPass
nordff = true;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
@ -163,7 +163,7 @@ struct PrepPass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))

8
techlibs/common/synth.cc
View file

@ -29,7 +29,7 @@ struct SynthPass : public ScriptPass
{
SynthPass() : ScriptPass("synth", "generic synthesis script") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -91,7 +91,7 @@ struct SynthPass : public ScriptPass
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap;
int lut;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_module.clear();
fsm_opts.clear();
@ -108,7 +108,7 @@ struct SynthPass : public ScriptPass
abc = "abc";
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -195,7 +195,7 @@ struct SynthPass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

4
techlibs/coolrunner2/coolrunner2_fixup.cc
View file

@ -112,7 +112,7 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
struct Coolrunner2FixupPass : public Pass {
Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" coolrunner2_fixup [options] [selection]\n");
@ -120,7 +120,7 @@ struct Coolrunner2FixupPass : public Pass {
log("Insert necessary buffer cells for CoolRunner-II architecture.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing COOLRUNNER2_FIXUP pass (insert necessary buffer cells for CoolRunner-II architecture).\n");
extra_args(args, 1, design);

4
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Coolrunner2SopPass : public Pass {
Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" coolrunner2_sop [options] [selection]\n");
@ -33,7 +33,7 @@ struct Coolrunner2SopPass : public Pass {
log("Break $sop cells into ANDTERM/ORTERM cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
extra_args(args, 1, design);

8
techlibs/coolrunner2/synth_coolrunner2.cc
View file

@ -29,7 +29,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
{
SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -66,7 +66,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
string top_opt, json_file;
bool flatten, retime;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
json_file = "";
@ -74,7 +74,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
retime = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -121,7 +121,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

8
techlibs/easic/synth_easic.cc
View file

@ -29,7 +29,7 @@ struct SynthEasicPass : public ScriptPass
{
SynthEasicPass() : ScriptPass("synth_easic", "synthesis for eASIC platform") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -67,7 +67,7 @@ struct SynthEasicPass : public ScriptPass
string top_opt, vlog_file, etools_path;
bool flatten, retime;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
vlog_file = "";
@ -76,7 +76,7 @@ struct SynthEasicPass : public ScriptPass
retime = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -127,7 +127,7 @@ struct SynthEasicPass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str());
string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str());

4
techlibs/ecp5/ecp5_ffinit.cc
View file

@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ecp5FfinitPass : public Pass {
Ecp5FfinitPass() : Pass("ecp5_ffinit", "ECP5: handle FF init values") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -36,7 +36,7 @@ struct Ecp5FfinitPass : public Pass {
log("If reset is not used, set the reset value to the init value, otherwise\n");
log("unmap out the reset (if not an async reset).\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ECP5_FFINIT pass (implement FF init values).\n");

4
techlibs/ecp5/ecp5_gsr.cc
View file

@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ecp5GsrPass : public Pass {
Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -40,7 +40,7 @@ struct Ecp5GsrPass : public Pass {
log("is not set, otherwise it will be resolved to \"DISABLED\".\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");

10
techlibs/ecp5/synth_ecp5.cc
View file

@ -30,12 +30,12 @@ struct SynthEcp5Pass : public ScriptPass
{
SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
void on_register() YS_OVERRIDE
void on_register() override
{
RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
}
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -112,7 +112,7 @@ struct SynthEcp5Pass : public ScriptPass
string top_opt, blif_file, edif_file, json_file;
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
blif_file = "";
@ -133,7 +133,7 @@ struct SynthEcp5Pass : public ScriptPass
nodsp = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -239,7 +239,7 @@ struct SynthEcp5Pass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

4
techlibs/efinix/efinix_fixcarry.cc
View file

@ -90,7 +90,7 @@ static void fix_carry_chain(Module *module)
struct EfinixCarryFixPass : public Pass {
EfinixCarryFixPass() : Pass("efinix_fixcarry", "Efinix: fix carry chain") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -99,7 +99,7 @@ struct EfinixCarryFixPass : public Pass {
log("Add Efinix adders to fix carry chain if needed.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n");

4
techlibs/efinix/efinix_gbuf.cc
View file

@ -87,7 +87,7 @@ static void handle_gbufs(Module *module)
struct EfinixGbufPass : public Pass {
EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -96,7 +96,7 @@ struct EfinixGbufPass : public Pass {
log("Add Efinix global clock buffers to top module as needed.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");

8
techlibs/efinix/synth_efinix.cc
View file

@ -30,7 +30,7 @@ struct SynthEfinixPass : public ScriptPass
{
SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -72,7 +72,7 @@ struct SynthEfinixPass : public ScriptPass
string top_opt, edif_file, json_file;
bool flatten, retime, nobram;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
edif_file = "";
@ -82,7 +82,7 @@ struct SynthEfinixPass : public ScriptPass
nobram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -137,7 +137,7 @@ struct SynthEfinixPass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

4
techlibs/gowin/determine_init.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct DetermineInitPass : public Pass {
DetermineInitPass() : Pass("determine_init", "Determine the init value of cells") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" determine_init [selection]\n");
@ -44,7 +44,7 @@ struct DetermineInitPass : public Pass {
return init;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing DETERMINE_INIT pass (determine init value for cells).\n");

8
techlibs/gowin/synth_gowin.cc
View file

@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass
{
SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -82,7 +82,7 @@ struct SynthGowinPass : public ScriptPass
string top_opt, vout_file;
bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
vout_file = "";
@ -96,7 +96,7 @@ struct SynthGowinPass : public ScriptPass
noiopads = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -167,7 +167,7 @@ struct SynthGowinPass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

4
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -91,7 +91,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
struct Greenpak4DffInvPass : public Pass {
Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" greenpak4_dffinv [options] [selection]\n");
@ -99,7 +99,7 @@ struct Greenpak4DffInvPass : public Pass {
log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");

8
techlibs/greenpak4/synth_greenpak4.cc
View file

@ -29,7 +29,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
{
SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -70,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
string top_opt, part, json_file;
bool flatten, retime;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
part = "SLG46621V";
@ -79,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
retime = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -133,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

4
techlibs/ice40/ice40_braminit.cc
View file

@ -128,7 +128,7 @@ static void run_ice40_braminit(Module *module)
struct Ice40BRAMInitPass : public Pass {
Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -138,7 +138,7 @@ struct Ice40BRAMInitPass : public Pass {
log("parameter and converts it into the required INIT_x attributes\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_BRAMINIT pass.\n");

4
techlibs/ice40/ice40_ffinit.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfinitPass : public Pass {
Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass {
log("nonzero init values.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");

4
techlibs/ice40/ice40_ffssr.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfssrPass : public Pass {
Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" ice40_ffssr [options] [selection]\n");
@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass {
log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");

4
techlibs/ice40/ice40_opt.cc
View file

@ -203,7 +203,7 @@ static void run_ice40_opts(Module *module)
struct Ice40OptPass : public Pass {
Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -220,7 +220,7 @@ struct Ice40OptPass : public Pass {
log(" while <changed design>\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string opt_expr_args = "-mux_undef -undriven";

10
techlibs/ice40/synth_ice40.cc
View file

@ -29,14 +29,14 @@ struct SynthIce40Pass : public ScriptPass
{
SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
void on_register() YS_OVERRIDE
void on_register() override
{
RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250";
RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400";
RTLIL::constpad["synth_ice40.abc9.u.W"] = "750";
}
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -119,7 +119,7 @@ struct SynthIce40Pass : public ScriptPass
bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap;
int min_ce_use;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
blif_file = "";
@ -140,7 +140,7 @@ struct SynthIce40Pass : public ScriptPass
device_opt = "hx";
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -262,7 +262,7 @@ struct SynthIce40Pass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
std::string define;
if (device_opt == "lp")

8
techlibs/intel/synth_intel.cc
View file

@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthIntelPass : public ScriptPass {
SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -81,7 +81,7 @@ struct SynthIntelPass : public ScriptPass {
string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram, iopads;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
family_opt = "max10";
@ -93,7 +93,7 @@ struct SynthIntelPass : public ScriptPass {
iopads = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -163,7 +163,7 @@ struct SynthIntelPass : public ScriptPass {
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin")) {
if (check_label("family"))

8
techlibs/intel_alm/synth_intel_alm.cc
View file

@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthIntelALMPass : public ScriptPass {
SynthIntelALMPass() : ScriptPass("synth_intel_alm", "synthesis for ALM-based Intel (Altera) FPGAs.") {}
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -74,7 +74,7 @@ struct SynthIntelALMPass : public ScriptPass {
string top_opt, family_opt, bram_type, vout_file;
bool flatten, quartus, nolutram, nobram;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
family_opt = "cyclonev";
@ -86,7 +86,7 @@ struct SynthIntelALMPass : public ScriptPass {
nobram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -153,7 +153,7 @@ struct SynthIntelALMPass : public ScriptPass {
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (help_mode) {
family_opt = "<family>";

4
techlibs/sf2/sf2_iobs.cc
View file

@ -155,7 +155,7 @@ static void handle_clkint(Module *module)
struct Sf2IobsPass : public Pass {
Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -167,7 +167,7 @@ struct Sf2IobsPass : public Pass {
log(" Insert PAD->global_net clock buffers\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool clkbuf_mode = false;

8
techlibs/sf2/synth_sf2.cc
View file

@ -29,7 +29,7 @@ struct SynthSf2Pass : public ScriptPass
{
SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -78,7 +78,7 @@ struct SynthSf2Pass : public ScriptPass
string top_opt, edif_file, vlog_file, json_file;
bool flatten, retime, iobs, clkbuf;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
edif_file = "";
@ -90,7 +90,7 @@ struct SynthSf2Pass : public ScriptPass
clkbuf = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@ -153,7 +153,7 @@ struct SynthSf2Pass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("begin"))
{

10
techlibs/xilinx/synth_xilinx.cc
View file

@ -30,13 +30,13 @@ struct SynthXilinxPass : public ScriptPass
{
SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
void on_register() YS_OVERRIDE
void on_register() override
{
RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
// to one LUT6 (instead of a LUT5 + LUT2)
}
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -149,7 +149,7 @@ struct SynthXilinxPass : public ScriptPass
int lut_size;
int widelut_size;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
top_opt = "-auto-top";
edif_file.clear();
@ -176,7 +176,7 @@ struct SynthXilinxPass : public ScriptPass
lut_size = 6;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string run_from, run_to;
clear_flags();
@ -337,7 +337,7 @@ struct SynthXilinxPass : public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
std::string lut_size_s = std::to_string(lut_size);
if (help_mode)

4
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -99,7 +99,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
struct XilinxDffOptPass : public Pass {
XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -113,7 +113,7 @@ struct XilinxDffOptPass : public Pass {
log(" Assume a LUT4-based device (instead of a LUT6-based device).\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n");