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Use C++11 final/override keywords.

This commit is contained in:
whitequark 2020-06-18 23:34:52 +00:00
parent dfde1cf1c5
commit 7191dd16f9
220 changed files with 540 additions and 548 deletions

View file

@ -244,7 +244,7 @@ static void test_abcloop()
struct TestAbcloopPass : public Pass {
TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass {
log(" use this value as rng seed value (default = unix time).\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design*) override
{
int num_iter = 100;
xorshift32_state = 0;

View file

@ -327,7 +327,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
struct TestAutotbBackend : public Backend {
TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -360,7 +360,7 @@ struct TestAutotbBackend : public Backend {
log(" the current system time.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
int num_iter = 1000;
int seed = 0;

View file

@ -652,7 +652,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
struct TestCellPass : public Pass {
TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -712,7 +712,7 @@ struct TestCellPass : public Pass {
log(" create a Verilog test bench to test simlib and write_verilog\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design*) override
{
int num_iter = 100;
std::string techmap_cmd = "techmap -assert";