mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 21:27:00 +00:00
Use C++11 final/override keywords.
This commit is contained in:
parent
dfde1cf1c5
commit
7191dd16f9
220 changed files with 540 additions and 548 deletions
|
@ -127,7 +127,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module)
|
|||
|
||||
struct MemoryUnpackPass : public Pass {
|
||||
MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { }
|
||||
void help() YS_OVERRIDE
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
|
@ -137,7 +137,7 @@ struct MemoryUnpackPass : public Pass {
|
|||
log("$memwr cells. It is the counterpart to the memory_collect pass.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
|
||||
log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
|
||||
extra_args(args, 1, design);
|
||||
for (auto module : design->selected_modules())
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue