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Use C++11 final/override keywords.

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This commit is contained in:
whitequark 2020-06-18 23:34:52 +00:00
parent dfde1cf1c5
commit 7191dd16f9
220 changed files with 540 additions and 548 deletions
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4
passes/hierarchy/hierarchy.cc
View file

@ -558,7 +558,7 @@ RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::stri
struct HierarchyPass : public Pass {
HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -639,7 +639,7 @@ struct HierarchyPass : public Pass {
log("in the current design.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");

4
passes/hierarchy/submod.cc
View file

@ -319,7 +319,7 @@ struct SubmodWorker
struct SubmodPass : public Pass {
SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -351,7 +351,7 @@ struct SubmodPass : public Pass {
log(" original module with original public names.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();

4
passes/hierarchy/uniquify.cc
View file

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct UniquifyPass : public Pass {
UniquifyPass() : Pass("uniquify", "create unique copies of modules") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -41,7 +41,7 @@ struct UniquifyPass : public Pass {
log("attribute set (the 'top' module is unique implicitly).\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");