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https://github.com/YosysHQ/yosys
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Use C++11 final/override keywords.
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parent
dfde1cf1c5
commit
7191dd16f9
220 changed files with 540 additions and 548 deletions
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@ -25,34 +25,34 @@ PRIVATE_NAMESPACE_BEGIN
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struct TraceMonitor : public RTLIL::Monitor
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{
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void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
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void notify_module_add(RTLIL::Module *module) override
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{
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log("#TRACE# Module add: %s\n", log_id(module));
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}
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void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
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void notify_module_del(RTLIL::Module *module) override
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{
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log("#TRACE# Module delete: %s\n", log_id(module));
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}
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void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE
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void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
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{
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log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
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}
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void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
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void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
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{
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log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
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}
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void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
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void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override
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{
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log("#TRACE# New connections in module %s:\n", log_id(module));
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for (auto &sigsig : sigsig_vec)
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log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
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}
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void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
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void notify_blackout(RTLIL::Module *module) override
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{
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log("#TRACE# Blackout in module %s:\n", log_id(module));
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}
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@ -60,7 +60,7 @@ struct TraceMonitor : public RTLIL::Monitor
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struct TracePass : public Pass {
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TracePass() : Pass("trace", "redirect command output to file") { }
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void help() YS_OVERRIDE
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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@ -70,7 +70,7 @@ struct TracePass : public Pass {
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log("the design in real time.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -96,7 +96,7 @@ struct TracePass : public Pass {
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struct DebugPass : public Pass {
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DebugPass() : Pass("debug", "run command with debug log messages enabled") { }
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void help() YS_OVERRIDE
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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@ -105,7 +105,7 @@ struct DebugPass : public Pass {
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log("Execute the specified command with debug log messages enabled\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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