mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-09 20:50:51 +00:00
Use C++11 final/override keywords.
This commit is contained in:
parent
dfde1cf1c5
commit
7191dd16f9
220 changed files with 540 additions and 548 deletions
|
@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN
|
|||
|
||||
struct MyPass : public Pass {
|
||||
MyPass() : Pass("my_cmd", "just a simple test") { }
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log("Arguments to my_cmd:\n");
|
||||
for (auto &arg : args)
|
||||
|
@ -22,7 +22,7 @@ struct MyPass : public Pass {
|
|||
|
||||
struct Test1Pass : public Pass {
|
||||
Test1Pass() : Pass("test1", "creating the absval module") { }
|
||||
void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
|
||||
void execute(std::vector<std::string>, RTLIL::Design *design) override
|
||||
{
|
||||
if (design->has("\\absval") != 0)
|
||||
log_error("A module with the name absval already exists!\n");
|
||||
|
@ -49,7 +49,7 @@ struct Test1Pass : public Pass {
|
|||
|
||||
struct Test2Pass : public Pass {
|
||||
Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
|
||||
void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
|
||||
void execute(std::vector<std::string>, RTLIL::Design *design) override
|
||||
{
|
||||
if (design->selection_stack.back().empty())
|
||||
log_cmd_error("This command can't operator on an empty selection!\n");
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue