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Use C++11 final/override keywords.
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parent
dfde1cf1c5
commit
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220 changed files with 540 additions and 548 deletions
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@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
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dict<SigBit, pool<SigBit>> db;
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FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
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SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
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SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
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db[from_sigbit].insert(to_sigbit);
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@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
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dict<SigBit, pool<SigBit>> db;
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RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
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SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
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SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
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db[to_sigbit].insert(from_sigbit);
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