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https://github.com/YosysHQ/yosys
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Use C++11 final/override keywords.
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parent
dfde1cf1c5
commit
7191dd16f9
220 changed files with 540 additions and 548 deletions
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@ -67,7 +67,7 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
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void help() YS_OVERRIDE
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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@ -232,7 +232,7 @@ struct VerilogFrontend : public Frontend {
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log("supported by the Yosys Verilog front-end.\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool flag_dump_ast1 = false;
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bool flag_dump_ast2 = false;
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@ -503,7 +503,7 @@ struct VerilogFrontend : public Frontend {
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struct VerilogDefaults : public Pass {
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VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
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void help() YS_OVERRIDE
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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@ -524,7 +524,7 @@ struct VerilogDefaults : public Pass {
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log("not imply -clear.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design*) override
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{
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if (args.size() < 2)
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cmd_error(args, 1, "Missing argument.");
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@ -561,7 +561,7 @@ struct VerilogDefaults : public Pass {
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struct VerilogDefines : public Pass {
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VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
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void help() YS_OVERRIDE
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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@ -583,7 +583,7 @@ struct VerilogDefines : public Pass {
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log(" list currently defined preprocessor symbols\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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