From 7186faa7e39d96a0be7ce8a40f52cc9dfc15f698 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 19 May 2026 20:49:59 +1200
Subject: [PATCH] verific: WIP mem index fixing

---
 frontends/verific/verific.cc | 45 ++++++++++++++++++++++++++++++++++--
 frontends/verific/verific.h  |  1 +
 2 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6a1c81aa4..5084e5428 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -562,6 +562,33 @@ RTLIL::SigSpec VerificImporter::operatorInput1(Instance *inst)
 	return sig;
 }
 
+RTLIL::SigSpec VerificImporter::operatorInput1_memaddr(Instance *inst, const Verific::TypeRange *typeRange)
+{
+	int idx = 0;
+	int width = typeRange->LogOfNumElements();
+	int i = 0;
+	while (typeRange->GetNext()) {
+		auto left = typeRange->LeftRangeBound();
+		auto right = typeRange->RightRangeBound();
+		auto elems = typeRange->IsUp() ? right - left + 1 : left - right + 1;
+		log(" ~ %d, %d:%d (%d) {%d}\n", idx, left, right, elems, i);
+		idx *= elems;
+
+		RTLIL::SigSpec sig;
+		for (unsigned int j = 0; j < typeRange->NumBits(); i++, j++) {
+			Net *net = inst->GetInput1Bit(i);
+			sig.append(netToSigBit(net));
+		}
+		auto lower = typeRange->IsUp() ? left : right;
+		sig.reverse();
+		log(" - %d += %s - %d {%d}\n", idx, log_signal(sig), lower, i);
+		idx += sig.as_int() - lower;
+		typeRange = typeRange->GetNext();
+	}
+	log_assert(i == int(inst->Input1Size()));
+	return RTLIL::SigSpec(idx, width);
+}
+
 RTLIL::SigSpec VerificImporter::operatorInput2(Instance *inst)
 {
 	RTLIL::SigSpec sig;
@@ -1625,6 +1652,15 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		{
 			RTLIL::Memory *memory = new RTLIL::Memory;
 			memory->name = RTLIL::escape_id(net->Name());
+			auto *typeRange = net->GetOrigTypeRange();
+			log("~**~ %d - %d\n", net->LeftIndex(), net->RightIndex());
+			log("     %s\n", typeRange->Dump());
+			log("     %d | %d : %d ; %d\n", typeRange->NumBits(), typeRange->LeftRangeBound(), typeRange->RightRangeBound(), typeRange->LogOfNumElements());
+			
+			auto *typeRangeNext = typeRange->GetNext();
+			log("     %s\n", typeRangeNext->Dump());
+			log("     %d | %d : %d ; %d\n", typeRangeNext->NumBits(), typeRangeNext->LeftRangeBound(), typeRangeNext->RightRangeBound(), typeRangeNext->LogOfNumElements());
+
 			log_assert(module->count_id(memory->name) == 0);
 			module->memories[memory->name] = memory;
 			import_attributes(memory->attributes, net, nl);
@@ -1932,12 +1968,15 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			if (!memory)
 				log_error("%sMemory net '%s' missing, possibly no driver, use verific -flatten.\n", announce_src_location(inst), inst->GetInput()->Name());
 
+			auto *typeRange = nl->GetTypeRange(inst->GetInput()->Name());
 			int numchunks = int(inst->OutputSize()) / memory->width;
 			int chunksbits = ceil_log2(numchunks);
+			log("!*~ numchunks: %d; chunksbits: %d; typeRange: %s\n", numchunks, chunksbits, typeRange->Dump());
 
 			for (int i = 0; i < numchunks; i++)
 			{
-				RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
+				RTLIL::SigSpec addr = {operatorInput1_memaddr(inst, typeRange), RTLIL::Const(i, chunksbits)};
+				log("  %d (%s)\n", addr.as_int(), log_signal(operatorInput1(inst)));
 				RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
 
 				RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
@@ -1962,12 +2001,14 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()), nullptr);
 			if (!memory)
 				log_error("%sMemory net '%s' missing, possibly no driver, use verific -flatten.\n", announce_src_location(inst), inst->GetInput()->Name());
+
+			auto *typeRange = nl->GetTypeRange(inst->GetOutput()->Name());
 			int numchunks = int(inst->Input2Size()) / memory->width;
 			int chunksbits = ceil_log2(numchunks);
 
 			for (int i = 0; i < numchunks; i++)
 			{
-				RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
+				RTLIL::SigSpec addr = {operatorInput1_memaddr(inst, typeRange), RTLIL::Const(i, chunksbits)};
 				RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
 
 				RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index f33a380f7..db81fefb7 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -88,6 +88,7 @@ struct VerificImporter
 	RTLIL::SigBit netToSigBit(Verific::Net *net);
 	RTLIL::SigSpec operatorInput(Verific::Instance *inst);
 	RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
+	RTLIL::SigSpec operatorInput1_memaddr(Verific::Instance *inst, const Verific::TypeRange *typeRange);
 	RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
 	RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
 	RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname);