From 716dbc92745aa8b41d85a60d50263433d5a79393 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Oct 2017 11:57:04 +0200
Subject: [PATCH] Revert 90be0d8 as it causes endless loops for some designs
---
passes/opt/opt_reduce.cc | 1 -
1 file changed, 1 deletion(-)
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 10bdf7221..eb9d02ad5 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -88,7 +88,6 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
- new_sig_a.sort_and_unify();
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
total_count++;