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RTLIL::S{0,1} -> State::S{0,1}

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This commit is contained in:
Eddie Hung 2019-08-07 11:12:38 -07:00
parent e6d5147214
commit 7164996921
15 changed files with 86 additions and 86 deletions
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2
backends/blif/blif.cc
View file

@ -377,7 +377,7 @@ struct BlifDumper
f << stringf("\n"); f << stringf("\n");
RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); RTLIL::SigSpec mask = cell->parameters.at("\\LUT");
for (int i = 0; i < (1 << width); i++) for (int i = 0; i < (1 << width); i++)
if (mask[i] == RTLIL::S1) { if (mask[i] == State::S1) {
for (int j = width-1; j >= 0; j--) { for (int j = width-1; j >= 0; j--) {
f << ((i>>j)&1 ? '1' : '0'); f << ((i>>j)&1 ? '1' : '0');
} }

8
backends/ilang/ilang_backend.cc
View file

@ -40,8 +40,8 @@ void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
log_assert(offset+i < (int)data.bits.size()); log_assert(offset+i < (int)data.bits.size());
switch (data.bits[offset+i]) { switch (data.bits[offset+i]) {
case RTLIL::S0: break; case State::S0: break;
case RTLIL::S1: val |= 1 << i; break; case State::S1: val |= 1 << i; break;
default: val = -1; break; default: val = -1; break;
} }
} }
@ -54,8 +54,8 @@ void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
for (int i = offset+width-1; i >= offset; i--) { for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size()); log_assert(i < (int)data.bits.size());
switch (data.bits[i]) { switch (data.bits[i]) {
case RTLIL::S0: f << stringf("0"); break; case State::S0: f << stringf("0"); break;
case RTLIL::S1: f << stringf("1"); break; case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break; case RTLIL::Sx: f << stringf("x"); break;
case RTLIL::Sz: f << stringf("z"); break; case RTLIL::Sz: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("-"); break; case RTLIL::Sa: f << stringf("-"); break;

2
backends/intersynth/intersynth.cc
View file

@ -183,7 +183,7 @@ struct IntersynthBackend : public Backend {
if (param.second.bits.size() != 32) { if (param.second.bits.size() != 32) {
node_code += stringf(" %s '", RTLIL::id2cstr(param.first)); node_code += stringf(" %s '", RTLIL::id2cstr(param.first));
for (int i = param.second.bits.size()-1; i >= 0; i--) for (int i = param.second.bits.size()-1; i >= 0; i--)
node_code += param.second.bits[i] == RTLIL::S1 ? "1" : "0"; node_code += param.second.bits[i] == State::S1 ? "1" : "0";
} else } else
node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int()); node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int());
} }

12
backends/verilog/verilog_backend.cc
View file

@ -200,9 +200,9 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
int32_t val = 0; int32_t val = 0;
for (int i = offset+width-1; i >= offset; i--) { for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size()); log_assert(i < (int)data.bits.size());
if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1) if (data.bits[i] != State::S0 && data.bits[i] != State::S1)
goto dump_hex; goto dump_hex;
if (data.bits[i] == RTLIL::S1) if (data.bits[i] == State::S1)
val |= 1 << (i - offset); val |= 1 << (i - offset);
} }
if (decimal) if (decimal)
@ -219,8 +219,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
for (int i = offset; i < offset+width; i++) { for (int i = offset; i < offset+width; i++) {
log_assert(i < (int)data.bits.size()); log_assert(i < (int)data.bits.size());
switch (data.bits[i]) { switch (data.bits[i]) {
case RTLIL::S0: bin_digits.push_back('0'); break; case State::S0: bin_digits.push_back('0'); break;
case RTLIL::S1: bin_digits.push_back('1'); break; case State::S1: bin_digits.push_back('1'); break;
case RTLIL::Sx: bin_digits.push_back('x'); break; case RTLIL::Sx: bin_digits.push_back('x'); break;
case RTLIL::Sz: bin_digits.push_back('z'); break; case RTLIL::Sz: bin_digits.push_back('z'); break;
case RTLIL::Sa: bin_digits.push_back('?'); break; case RTLIL::Sa: bin_digits.push_back('?'); break;
@ -273,8 +273,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
for (int i = offset+width-1; i >= offset; i--) { for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size()); log_assert(i < (int)data.bits.size());
switch (data.bits[i]) { switch (data.bits[i]) {
case RTLIL::S0: f << stringf("0"); break; case State::S0: f << stringf("0"); break;
case RTLIL::S1: f << stringf("1"); break; case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break; case RTLIL::Sx: f << stringf("x"); break;
case RTLIL::Sz: f << stringf("z"); break; case RTLIL::Sz: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("?"); break; case RTLIL::Sa: f << stringf("?"); break;

14
frontends/ast/ast.cc
View file

@ -283,8 +283,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
if (!bits.empty()) { if (!bits.empty()) {
fprintf(f, " bits='"); fprintf(f, " bits='");
for (size_t i = bits.size(); i > 0; i--) for (size_t i = bits.size(); i > 0; i--)
fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' : fprintf(f, "%c", bits[i-1] == State::S0 ? '0' :
bits[i-1] == RTLIL::S1 ? '1' : bits[i-1] == State::S1 ? '1' :
bits[i-1] == RTLIL::Sx ? 'x' : bits[i-1] == RTLIL::Sx ? 'x' :
bits[i-1] == RTLIL::Sz ? 'z' : '?'); bits[i-1] == RTLIL::Sz ? 'z' : '?');
fprintf(f, "'(%d)", GetSize(bits)); fprintf(f, "'(%d)", GetSize(bits));
@ -716,7 +716,7 @@ AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
node->integer = v; node->integer = v;
node->is_signed = is_signed; node->is_signed = is_signed;
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0); node->bits.push_back((v & 1) ? State::S1 : State::S0);
v = v >> 1; v = v >> 1;
} }
node->range_valid = true; node->range_valid = true;
@ -733,9 +733,9 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe
node->bits = v; node->bits = v;
for (size_t i = 0; i < 32; i++) { for (size_t i = 0; i < 32; i++) {
if (i < node->bits.size()) if (i < node->bits.size())
node->integer |= (node->bits[i] == RTLIL::S1) << i; node->integer |= (node->bits[i] == State::S1) << i;
else if (is_signed && !node->bits.empty()) else if (is_signed && !node->bits.empty())
node->integer |= (node->bits.back() == RTLIL::S1) << i; node->integer |= (node->bits.back() == State::S1) << i;
} }
node->range_valid = true; node->range_valid = true;
node->range_left = node->bits.size()-1; node->range_left = node->bits.size()-1;
@ -767,7 +767,7 @@ AstNode *AstNode::mkconst_str(const std::string &str)
for (size_t i = 0; i < str.size(); i++) { for (size_t i = 0; i < str.size(); i++) {
unsigned char ch = str[str.size() - i - 1]; unsigned char ch = str[str.size() - i - 1];
for (int j = 0; j < 8; j++) { for (int j = 0; j < 8; j++) {
data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0); data.push_back((ch & 1) ? State::S1 : State::S0);
ch = ch >> 1; ch = ch >> 1;
} }
} }
@ -780,7 +780,7 @@ AstNode *AstNode::mkconst_str(const std::string &str)
bool AstNode::bits_only_01() const bool AstNode::bits_only_01() const
{ {
for (auto bit : bits) for (auto bit : bits)
if (bit != RTLIL::S0 && bit != RTLIL::S1) if (bit != State::S0 && bit != State::S1)
return false; return false;
return true; return true;
} }

24
frontends/verilog/const2ast.cc
View file

@ -99,7 +99,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
if (base == 10) { if (base == 10) {
while (!digits.empty()) while (!digits.empty())
data.push_back(my_decimal_div_by_two(digits) ? RTLIL::S1 : RTLIL::S0); data.push_back(my_decimal_div_by_two(digits) ? State::S1 : State::S0);
} else { } else {
int bits_per_digit = my_ilog2(base-1); int bits_per_digit = my_ilog2(base-1);
for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) { for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
@ -115,17 +115,17 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
else if (*it == 0xf2) else if (*it == 0xf2)
data.push_back(RTLIL::Sa); data.push_back(RTLIL::Sa);
else else
data.push_back((*it & bitmask) ? RTLIL::S1 : RTLIL::S0); data.push_back((*it & bitmask) ? State::S1 : State::S0);
} }
} }
} }
int len = GetSize(data); int len = GetSize(data);
RTLIL::State msb = data.empty() ? RTLIL::S0 : data.back(); RTLIL::State msb = data.empty() ? State::S0 : data.back();
if (len_in_bits < 0) { if (len_in_bits < 0) {
if (len < 32) if (len < 32)
data.resize(32, msb == RTLIL::S0 || msb == RTLIL::S1 ? RTLIL::S0 : msb); data.resize(32, msb == State::S0 || msb == State::S1 ? RTLIL::S0 : msb);
return; return;
} }
@ -133,11 +133,11 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len); log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len);
for (len = len - 1; len >= 0; len--) for (len = len - 1; len >= 0; len--)
if (data[len] == RTLIL::S1) if (data[len] == State::S1)
break; break;
if (msb == RTLIL::S0 || msb == RTLIL::S1) { if (msb == State::S0 || msb == State::S1) {
len += 1; len += 1;
data.resize(len_in_bits, RTLIL::S0); data.resize(len_in_bits, State::S0);
} else { } else {
len += 2; len += 2;
data.resize(len_in_bits, msb); data.resize(len_in_bits, msb);
@ -169,7 +169,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
for (int i = 0; i < len; i++) { for (int i = 0; i < len; i++) {
unsigned char ch = str[len - i]; unsigned char ch = str[len - i];
for (int j = 0; j < 8; j++) { for (int j = 0; j < 8; j++) {
data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0); data.push_back((ch & 1) ? State::S1 : State::S0);
ch = ch >> 1; ch = ch >> 1;
} }
} }
@ -190,8 +190,8 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
if (*endptr == 0) { if (*endptr == 0) {
std::vector<RTLIL::State> data; std::vector<RTLIL::State> data;
my_strtobin(data, str, -1, 10, case_type, false); my_strtobin(data, str, -1, 10, case_type, false);
if (data.back() == RTLIL::S1) if (data.back() == State::S1)
data.push_back(RTLIL::S0); data.push_back(State::S0);
return AstNode::mkconst_bits(data, true); return AstNode::mkconst_bits(data, true);
} }
@ -237,8 +237,8 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
} }
} }
if (len_in_bits < 0) { if (len_in_bits < 0) {
if (is_signed && data.back() == RTLIL::S1) if (is_signed && data.back() == State::S1)
data.push_back(RTLIL::S0); data.push_back(State::S0);
} }
return AstNode::mkconst_bits(data, is_signed, is_unsized); return AstNode::mkconst_bits(data, is_signed, is_unsized);
} }

12
kernel/rtlil.cc
View file

@ -47,7 +47,7 @@ RTLIL::Const::Const(std::string str)
for (int i = str.size()-1; i >= 0; i--) { for (int i = str.size()-1; i >= 0; i--) {
unsigned char ch = str[i]; unsigned char ch = str[i];
for (int j = 0; j < 8; j++) { for (int j = 0; j < 8; j++) {
bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0); bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
ch = ch >> 1; ch = ch >> 1;
} }
} }
@ -57,7 +57,7 @@ RTLIL::Const::Const(int val, int width)
{ {
flags = RTLIL::CONST_FLAG_NONE; flags = RTLIL::CONST_FLAG_NONE;
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0); bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1; val = val >> 1;
} }
} }
@ -73,7 +73,7 @@ RTLIL::Const::Const(const std::vector<bool> &bits)
{ {
flags = RTLIL::CONST_FLAG_NONE; flags = RTLIL::CONST_FLAG_NONE;
for (auto b : bits) for (auto b : bits)
this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0); this->bits.push_back(b ? State::S1 : State::S0);
} }
RTLIL::Const::Const(const RTLIL::Const &c) RTLIL::Const::Const(const RTLIL::Const &c)
@ -106,7 +106,7 @@ bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
bool RTLIL::Const::as_bool() const bool RTLIL::Const::as_bool() const
{ {
for (size_t i = 0; i < bits.size(); i++) for (size_t i = 0; i < bits.size(); i++)
if (bits[i] == RTLIL::S1) if (bits[i] == State::S1)
return true; return true;
return false; return false;
} }
@ -115,9 +115,9 @@ int RTLIL::Const::as_int(bool is_signed) const
{ {
int32_t ret = 0; int32_t ret = 0;
for (size_t i = 0; i < bits.size() && i < 32; i++) for (size_t i = 0; i < bits.size() && i < 32; i++)
if (bits[i] == RTLIL::S1) if (bits[i] == State::S1)
ret |= 1 << i; ret |= 1 << i;
if (is_signed && bits.back() == RTLIL::S1) if (is_signed && bits.back() == State::S1)
for (size_t i = bits.size(); i < 32; i++) for (size_t i = bits.size(); i < 32; i++)
ret |= 1 << i; ret |= 1 << i;
return ret; return ret;

28
passes/fsm/fsm_extract.cc
View file

@ -168,7 +168,7 @@ undef_bit_in_next_state:
ctrl_in_bit_indices[ctrl_in[i]] = i; ctrl_in_bit_indices[ctrl_in[i]] = i;
for (auto &it : ctrl_in_bit_indices) for (auto &it : ctrl_in_bit_indices)
if (tr.ctrl_in.bits.at(it.second) == RTLIL::S1 && exclusive_ctrls.count(it.first) != 0) if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
for (auto &dc_bit : exclusive_ctrls.at(it.first)) for (auto &dc_bit : exclusive_ctrls.at(it.first))
if (ctrl_in_bit_indices.count(dc_bit)) if (ctrl_in_bit_indices.count(dc_bit))
tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa; tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
@ -216,13 +216,13 @@ undef_bit_in_next_state:
ce.push(); ce.push();
dont_care.append(undef); dont_care.append(undef);
ce.set(undef, constval.as_const()); ce.set(undef, constval.as_const());
if (exclusive_ctrls.count(undef) && constval == RTLIL::S1) if (exclusive_ctrls.count(undef) && constval == State::S1)
for (auto &bit : exclusive_ctrls.at(undef)) { for (auto &bit : exclusive_ctrls.at(undef)) {
RTLIL::SigSpec bitval = bit; RTLIL::SigSpec bitval = bit;
if (ce.eval(bitval) && bitval != RTLIL::S0) if (ce.eval(bitval) && bitval != State::S0)
goto found_contradiction_1; goto found_contradiction_1;
else else
ce.set(bit, RTLIL::S0); ce.set(bit, State::S0);
} }
find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
found_contradiction_1: found_contradiction_1:
@ -231,21 +231,21 @@ undef_bit_in_next_state:
else else
{ {
ce.push(), ce_nostop.push(); ce.push(), ce_nostop.push();
ce.set(undef, RTLIL::S0); ce.set(undef, State::S0);
ce_nostop.set(undef, RTLIL::S0); ce_nostop.set(undef, State::S0);
find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
ce.pop(), ce_nostop.pop(); ce.pop(), ce_nostop.pop();
ce.push(), ce_nostop.push(); ce.push(), ce_nostop.push();
ce.set(undef, RTLIL::S1); ce.set(undef, State::S1);
ce_nostop.set(undef, RTLIL::S1); ce_nostop.set(undef, State::S1);
if (exclusive_ctrls.count(undef)) if (exclusive_ctrls.count(undef))
for (auto &bit : exclusive_ctrls.at(undef)) { for (auto &bit : exclusive_ctrls.at(undef)) {
RTLIL::SigSpec bitval = bit; RTLIL::SigSpec bitval = bit;
if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != RTLIL::S0) if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != State::S0)
goto found_contradiction_2; goto found_contradiction_2;
else else
ce.set(bit, RTLIL::S0), ce_nostop.set(bit, RTLIL::S0); ce.set(bit, State::S0), ce_nostop.set(bit, RTLIL::S0);
} }
find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
found_contradiction_2: found_contradiction_2:
@ -263,8 +263,8 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width); RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width);
RTLIL::Const reset_state(RTLIL::State::Sx, wire->width); RTLIL::Const reset_state(RTLIL::State::Sx, wire->width);
RTLIL::SigSpec clk = RTLIL::S0; RTLIL::SigSpec clk = State::S0;
RTLIL::SigSpec arst = RTLIL::S0; RTLIL::SigSpec arst = State::S0;
bool clk_polarity = true; bool clk_polarity = true;
bool arst_polarity = true; bool arst_polarity = true;
@ -371,8 +371,8 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
fsm_cell->setPort("\\CLK", clk); fsm_cell->setPort("\\CLK", clk);
fsm_cell->setPort("\\ARST", arst); fsm_cell->setPort("\\ARST", arst);
fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? RTLIL::S1 : RTLIL::S0; fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0;
fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? RTLIL::S1 : RTLIL::S0; fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0;
fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort("\\CTRL_IN", ctrl_in);
fsm_cell->setPort("\\CTRL_OUT", ctrl_out); fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());

2
passes/opt/muxpack.cc
View file

@ -49,7 +49,7 @@ struct ExclusiveDatabase
} }
else if (cell->type == "$logic_not") { else if (cell->type == "$logic_not") {
nonconst_sig = sigmap(cell->getPort("\\A")); nonconst_sig = sigmap(cell->getPort("\\A"));
const_sig = Const(RTLIL::S0, GetSize(nonconst_sig)); const_sig = Const(State::S0, GetSize(nonconst_sig));
y_port = sigmap(cell->getPort("\\Y")); y_port = sigmap(cell->getPort("\\Y"));
} }
else if (cell->type == "$reduce_or") { else if (cell->type == "$reduce_or") {

2
passes/techmap/abc9.cc
View file

@ -593,7 +593,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
c->setPort("\\Y", module->addWire(NEW_ID)); c->setPort("\\Y", module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire); log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1); module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
} }
else if (!lut_costs.empty() || !lut_file.empty()) { else if (!lut_costs.empty() || !lut_file.empty()) {
RTLIL::Cell* driver_lut = nullptr; RTLIL::Cell* driver_lut = nullptr;

12
passes/techmap/alumacc.cc
View file

@ -315,7 +315,7 @@ struct AlumaccWorker
} }
if (subtract_b) if (subtract_b)
C.append(RTLIL::S1); C.append(State::S1);
if (GetSize(C) > 1) if (GetSize(C) > 1)
goto next_macc; goto next_macc;
@ -402,7 +402,7 @@ struct AlumaccWorker
alunode_t *n = nullptr; alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)]) for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) { if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node; n = node;
break; break;
} }
@ -411,7 +411,7 @@ struct AlumaccWorker
n = new alunode_t; n = new alunode_t;
n->a = A; n->a = A;
n->b = B; n->b = B;
n->c = RTLIL::S1; n->c = State::S1;
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B))); n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed; n->is_signed = is_signed;
n->invert_b = true; n->invert_b = true;
@ -440,7 +440,7 @@ struct AlumaccWorker
alunode_t *n = nullptr; alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)]) for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) { if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node; n = node;
break; break;
} }
@ -484,8 +484,8 @@ struct AlumaccWorker
n->alu_cell->setPort("\\A", n->a); n->alu_cell->setPort("\\A", n->a);
n->alu_cell->setPort("\\B", n->b); n->alu_cell->setPort("\\B", n->b);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0); n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0); n->alu_cell->setPort("\\BI", n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort("\\Y", n->y); n->alu_cell->setPort("\\Y", n->y);
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y))); n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y))); n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y)));

2
passes/techmap/dff2dffe.cc
View file

@ -167,7 +167,7 @@ struct Dff2dffeWorker
} }
if (GetSize(or_input) == 0) if (GetSize(or_input) == 0)
return RTLIL::S1; return State::S1;
if (GetSize(or_input) == 1) if (GetSize(or_input) == 1)
return or_input; return or_input;

16
passes/techmap/maccmap.cc
View file

@ -36,7 +36,7 @@ struct MaccmapWorker
void add(RTLIL::SigBit bit, int position) void add(RTLIL::SigBit bit, int position)
{ {
if (position >= width || bit == RTLIL::S0) if (position >= width || bit == State::S0)
return; return;
if (bits.at(position).count(bit)) { if (bits.at(position).count(bit)) {
@ -53,7 +53,7 @@ struct MaccmapWorker
if (do_subtract) { if (do_subtract) {
a = module->Not(NEW_ID, a); a = module->Not(NEW_ID, a);
add(RTLIL::S1, 0); add(State::S1, 0);
} }
for (int i = 0; i < width; i++) for (int i = 0; i < width; i++)
@ -80,7 +80,7 @@ struct MaccmapWorker
else else
{ {
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {a.extract(0, width-1), RTLIL::S0}; a = {a.extract(0, width-1), State::S0};
} }
} }
@ -88,10 +88,10 @@ struct MaccmapWorker
{ {
int start_index = 0, stop_index = GetSize(in1); int start_index = 0, stop_index = GetSize(in1);
while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0) while (start_index < stop_index && in1[start_index] == State::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
start_index++; start_index++;
while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0) while (start_index < stop_index && in1[stop_index-1] == State::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
stop_index--; stop_index--;
if (start_index == stop_index) if (start_index == stop_index)
@ -222,7 +222,7 @@ struct MaccmapWorker
RTLIL::SigSpec in3 = summands[i+2]; RTLIL::SigSpec in3 = summands[i+2];
RTLIL::SigSpec out1, out2; RTLIL::SigSpec out1, out2;
fulladd(in1, in2, in3, out1, out2); fulladd(in1, in2, in3, out1, out2);
RTLIL::SigBit extra_bit = RTLIL::S0; RTLIL::SigBit extra_bit = State::S0;
if (!tree_sum_bits.empty()) { if (!tree_sum_bits.empty()) {
extra_bit = tree_sum_bits.back(); extra_bit = tree_sum_bits.back();
tree_sum_bits.pop_back(); tree_sum_bits.pop_back();
@ -240,8 +240,8 @@ struct MaccmapWorker
RTLIL::Cell *c = module->addCell(NEW_ID, "$alu"); RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
c->setPort("\\A", summands.front()); c->setPort("\\A", summands.front());
c->setPort("\\B", summands.back()); c->setPort("\\B", summands.back());
c->setPort("\\CI", RTLIL::S0); c->setPort("\\CI", State::S0);
c->setPort("\\BI", RTLIL::S0); c->setPort("\\BI", State::S0);
c->setPort("\\Y", module->addWire(NEW_ID, width)); c->setPort("\\Y", module->addWire(NEW_ID, width));
c->setPort("\\X", module->addWire(NEW_ID, width)); c->setPort("\\X", module->addWire(NEW_ID, width));
c->setPort("\\CO", module->addWire(NEW_ID, width)); c->setPort("\\CO", module->addWire(NEW_ID, width));

34
passes/tests/test_cell.cc
View file

@ -186,7 +186,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
RTLIL::SigSpec config; RTLIL::SigSpec config;
for (int i = 0; i < (1 << width); i++) for (int i = 0; i < (1 << width); i++)
config.append(xorshift32(2) ? RTLIL::S1 : RTLIL::S0); config.append(xorshift32(2) ? State::S1 : State::S0);
cell->setParam("\\LUT", config.as_const()); cell->setParam("\\LUT", config.as_const());
} }
@ -209,16 +209,16 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
for (int i = 0; i < width*depth; i++) for (int i = 0; i < width*depth; i++)
switch (xorshift32(3)) { switch (xorshift32(3)) {
case 0: case 0:
config.append(RTLIL::S1); config.append(State::S1);
config.append(RTLIL::S0); config.append(State::S0);
break; break;
case 1: case 1:
config.append(RTLIL::S0); config.append(State::S0);
config.append(RTLIL::S1); config.append(State::S1);
break; break;
case 2: case 2:
config.append(RTLIL::S0); config.append(State::S0);
config.append(RTLIL::S0); config.append(State::S0);
break; break;
} }
@ -308,18 +308,18 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
case 0: case 0:
n = xorshift32(GetSize(sig) + 1); n = xorshift32(GetSize(sig) + 1);
for (int i = 0; i < n; i++) for (int i = 0; i < n; i++)
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
break; break;
case 1: case 1:
n = xorshift32(GetSize(sig) + 1); n = xorshift32(GetSize(sig) + 1);
for (int i = n; i < GetSize(sig); i++) for (int i = n; i < GetSize(sig); i++)
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
break; break;
case 2: case 2:
n = xorshift32(GetSize(sig)); n = xorshift32(GetSize(sig));
m = xorshift32(GetSize(sig)); m = xorshift32(GetSize(sig));
for (int i = min(n, m); i < max(n, m); i++) for (int i = min(n, m); i < max(n, m); i++)
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
break; break;
} }
@ -491,7 +491,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
RTLIL::Const in_value; RTLIL::Const in_value;
for (int i = 0; i < GetSize(gold_wire); i++) for (int i = 0; i < GetSize(gold_wire); i++)
in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0); in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0);
if (xorshift32(4) == 0) { if (xorshift32(4) == 0) {
int inv_chance = 1 + xorshift32(8); int inv_chance = 1 + xorshift32(8);
@ -591,11 +591,11 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
} }
for (int i = 0; i < GetSize(out_sig); i++) { for (int i = 0; i < GetSize(out_sig); i++) {
if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) if (out_val[i] != State::S0 && out_val[i] != State::S1)
continue; continue;
if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false) if (out_val[i] == State::S0 && sat1_model_value.at(i) == false)
continue; continue;
if (out_val[i] == RTLIL::S1 && sat1_model_value.at(i) == true) if (out_val[i] == State::S1 && sat1_model_value.at(i) == true)
continue; continue;
log_error("Mismatch in sat model 1 (no undef modeling) output!\n"); log_error("Mismatch in sat model 1 (no undef modeling) output!\n");
} }
@ -627,12 +627,12 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
for (int i = 0; i < GetSize(out_sig); i++) { for (int i = 0; i < GetSize(out_sig); i++) {
if (sat2_model_value.at(GetSize(out_sig) + i)) { if (sat2_model_value.at(GetSize(out_sig) + i)) {
if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) if (out_val[i] != State::S0 && out_val[i] != State::S1)
continue; continue;
} else { } else {
if (out_val[i] == RTLIL::S0 && sat2_model_value.at(i) == false) if (out_val[i] == State::S0 && sat2_model_value.at(i) == false)
continue; continue;
if (out_val[i] == RTLIL::S1 && sat2_model_value.at(i) == true) if (out_val[i] == State::S1 && sat2_model_value.at(i) == true)
continue; continue;
} }
log_error("Mismatch in sat model 2 (undef modeling) output!\n"); log_error("Mismatch in sat model 2 (undef modeling) output!\n");

2
techlibs/ice40/ice40_opt.cc
View file

@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module)
log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output)); log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut"; cell->type = "$lut";
cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] }); cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
cell->setPort("\\Y", cell->getPort("\\O")); cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B"); cell->unsetPort("\\B");
cell->unsetPort("\\CI"); cell->unsetPort("\\CI");