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RTLIL::S{0,1} -> State::S{0,1}

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This commit is contained in:
Eddie Hung 2019-08-07 11:12:38 -07:00
parent e6d5147214
commit 7164996921
15 changed files with 86 additions and 86 deletions
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2
passes/techmap/abc9.cc
View file

@ -593,7 +593,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
c->setPort("\\Y", module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
}
else if (!lut_costs.empty() || !lut_file.empty()) {
RTLIL::Cell* driver_lut = nullptr;

12
passes/techmap/alumacc.cc
View file

@ -315,7 +315,7 @@ struct AlumaccWorker
}
if (subtract_b)
C.append(RTLIL::S1);
C.append(State::S1);
if (GetSize(C) > 1)
goto next_macc;
@ -402,7 +402,7 @@ struct AlumaccWorker
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node;
break;
}
@ -411,7 +411,7 @@ struct AlumaccWorker
n = new alunode_t;
n->a = A;
n->b = B;
n->c = RTLIL::S1;
n->c = State::S1;
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
@ -440,7 +440,7 @@ struct AlumaccWorker
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node;
break;
}
@ -484,8 +484,8 @@ struct AlumaccWorker
n->alu_cell->setPort("\\A", n->a);
n->alu_cell->setPort("\\B", n->b);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort("\\Y", n->y);
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y)));

2
passes/techmap/dff2dffe.cc
View file

@ -167,7 +167,7 @@ struct Dff2dffeWorker
}
if (GetSize(or_input) == 0)
return RTLIL::S1;
return State::S1;
if (GetSize(or_input) == 1)
return or_input;

16
passes/techmap/maccmap.cc
View file

@ -36,7 +36,7 @@ struct MaccmapWorker
void add(RTLIL::SigBit bit, int position)
{
if (position >= width || bit == RTLIL::S0)
if (position >= width || bit == State::S0)
return;
if (bits.at(position).count(bit)) {
@ -53,7 +53,7 @@ struct MaccmapWorker
if (do_subtract) {
a = module->Not(NEW_ID, a);
add(RTLIL::S1, 0);
add(State::S1, 0);
}
for (int i = 0; i < width; i++)
@ -80,7 +80,7 @@ struct MaccmapWorker
else
{
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {a.extract(0, width-1), RTLIL::S0};
a = {a.extract(0, width-1), State::S0};
}
}
@ -88,10 +88,10 @@ struct MaccmapWorker
{
int start_index = 0, stop_index = GetSize(in1);
while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
while (start_index < stop_index && in1[start_index] == State::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
start_index++;
while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
while (start_index < stop_index && in1[stop_index-1] == State::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
stop_index--;
if (start_index == stop_index)
@ -222,7 +222,7 @@ struct MaccmapWorker
RTLIL::SigSpec in3 = summands[i+2];
RTLIL::SigSpec out1, out2;
fulladd(in1, in2, in3, out1, out2);
RTLIL::SigBit extra_bit = RTLIL::S0;
RTLIL::SigBit extra_bit = State::S0;
if (!tree_sum_bits.empty()) {
extra_bit = tree_sum_bits.back();
tree_sum_bits.pop_back();
@ -240,8 +240,8 @@ struct MaccmapWorker
RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
c->setPort("\\A", summands.front());
c->setPort("\\B", summands.back());
c->setPort("\\CI", RTLIL::S0);
c->setPort("\\BI", RTLIL::S0);
c->setPort("\\CI", State::S0);
c->setPort("\\BI", State::S0);
c->setPort("\\Y", module->addWire(NEW_ID, width));
c->setPort("\\X", module->addWire(NEW_ID, width));
c->setPort("\\CO", module->addWire(NEW_ID, width));