mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-20 22:25:49 +00:00
Merge from upstream
This commit is contained in:
commit
71586d39b0
14 changed files with 720 additions and 260 deletions
|
|
@ -11,8 +11,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
|
|||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd fsm # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 2 t:LUT2
|
||||
select -assert-count 4 t:LUT3
|
||||
select -assert-count 4 t:dffepc
|
||||
select -assert-count 1 t:logic_0
|
||||
select -assert-count 1 t:logic_1
|
||||
|
|
|
|||
|
|
@ -69,7 +69,8 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
|
|||
design -load postopt
|
||||
cd cascade
|
||||
select -assert-count 2 t:DSP48E1
|
||||
select -assert-none t:DSP48E1 t:BUFG %% t:* %D
|
||||
# TODO Disabled check, FDREs emitted due to order sensitivity
|
||||
# select -assert-none t:DSP48E1 t:BUFG %% t:* %D
|
||||
# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
|
||||
# (see above for explanation)
|
||||
select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
|
||||
|
|
|
|||
|
|
@ -361,6 +361,36 @@ namespace RTLIL {
|
|||
EXPECT_FALSE(Const().is_onehot(&pos));
|
||||
}
|
||||
|
||||
TEST_F(KernelRtlilTest, OwningIdString) {
|
||||
OwningIdString own("\\figblortle");
|
||||
OwningIdString::collect_garbage();
|
||||
EXPECT_EQ(own.str(), "\\figblortle");
|
||||
}
|
||||
|
||||
TEST_F(KernelRtlilTest, LookupAutoidxId) {
|
||||
IdString id = NEW_ID;
|
||||
IdString id2 = IdString(id.str());
|
||||
EXPECT_EQ(id, id2);
|
||||
}
|
||||
|
||||
TEST_F(KernelRtlilTest, NewIdBeginsWith) {
|
||||
IdString id = NEW_ID;
|
||||
EXPECT_TRUE(id.begins_with("$auto"));
|
||||
EXPECT_FALSE(id.begins_with("xyz"));
|
||||
EXPECT_TRUE(id.begins_with("$auto$"));
|
||||
EXPECT_FALSE(id.begins_with("abcdefghijklmn"));
|
||||
EXPECT_TRUE(id.begins_with("$auto$rtlilTest"));
|
||||
EXPECT_FALSE(id.begins_with("$auto$rtlilX"));
|
||||
}
|
||||
|
||||
TEST_F(KernelRtlilTest, NewIdIndexing) {
|
||||
IdString id = NEW_ID;
|
||||
std::string str = id.str();
|
||||
for (int i = 0; i < GetSize(str) + 1; ++i) {
|
||||
EXPECT_EQ(id[i], str.c_str()[i]);
|
||||
}
|
||||
}
|
||||
|
||||
class WireRtlVsHdlIndexConversionTest :
|
||||
public KernelRtlilTest,
|
||||
public testing::WithParamInterface<std::tuple<bool, int, int>>
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue