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write_cxxrtl: support initial $print
cells.
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d493225313
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@ -1291,8 +1291,9 @@ struct CxxrtlWorker {
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log_assert(!for_debug);
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log_assert(!for_debug);
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// Sync $print cells are grouped into PRINT_SYNC nodes in the FlowGraph.
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// Sync $print cells are grouped into PRINT_SYNC nodes in the FlowGraph.
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log_assert(!cell->getParam(ID::TRG_ENABLE).as_bool());
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log_assert(!cell->getParam(ID::TRG_ENABLE).as_bool() || (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0));
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if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async $print cell
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f << indent << "auto " << mangle(cell) << "_curr = ";
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f << indent << "auto " << mangle(cell) << "_curr = ";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << ".concat(";
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f << ".concat(";
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@ -1305,6 +1306,14 @@ struct CxxrtlWorker {
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f << indent << mangle(cell) << " = " << mangle(cell) << "_curr;\n";
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f << indent << mangle(cell) << " = " << mangle(cell) << "_curr;\n";
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dec_indent();
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dec_indent();
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f << indent << "}\n";
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f << indent << "}\n";
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} else { // initial $print cell
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f << indent << "if (!" << mangle(cell) << ") {\n";
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inc_indent();
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dump_print(cell);
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f << indent << mangle(cell) << " = value<1>{1u};\n";
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dec_indent();
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f << indent << "}\n";
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}
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// Flip-flops
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// Flip-flops
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} else if (is_ff_cell(cell->type)) {
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} else if (is_ff_cell(cell->type)) {
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log_assert(!for_debug);
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log_assert(!for_debug);
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@ -2002,8 +2011,11 @@ struct CxxrtlWorker {
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}
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}
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}
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}
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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// Certain $print cells have additional state, which must be reset as well.
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if (cell->type == ID($print) && !cell->getParam(ID::TRG_ENABLE).as_bool())
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if (cell->type == ID($print) && !cell->getParam(ID::TRG_ENABLE).as_bool())
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f << indent << mangle(cell) << " = value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << ">();\n";
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f << indent << mangle(cell) << " = value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << ">();\n";
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if (cell->type == ID($print) && cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
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f << indent << mangle(cell) << " = value<1>();\n";
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if (is_internal_cell(cell->type))
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if (is_internal_cell(cell->type))
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continue;
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continue;
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f << indent << mangle(cell);
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f << indent << mangle(cell);
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@ -2432,11 +2444,11 @@ struct CxxrtlWorker {
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f << "\n";
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f << "\n";
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bool has_cells = false;
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bool has_cells = false;
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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if (cell->type == ID($print) && !cell->getParam(ID::TRG_ENABLE).as_bool()) {
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// Certain $print cells have additional state, which requires storage.
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// comb $print cell -- store the last EN/ARGS values to know when they change.
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if (cell->type == ID($print) && !cell->getParam(ID::TRG_ENABLE).as_bool())
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dump_attrs(cell);
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f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n";
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f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n";
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}
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if (cell->type == ID($print) && cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
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f << indent << "value<1> " << mangle(cell) << ";\n";
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if (is_internal_cell(cell->type))
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if (is_internal_cell(cell->type))
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continue;
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continue;
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dump_attrs(cell);
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dump_attrs(cell);
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@ -2967,7 +2979,8 @@ struct CxxrtlWorker {
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if (live_nodes[node]) {
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if (live_nodes[node]) {
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if (node->type == FlowGraph::Node::Type::CELL_EVAL &&
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if (node->type == FlowGraph::Node::Type::CELL_EVAL &&
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node->cell->type == ID($print) &&
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node->cell->type == ID($print) &&
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node->cell->getParam(ID::TRG_ENABLE).as_bool())
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node->cell->getParam(ID::TRG_ENABLE).as_bool() &&
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node->cell->getParam(ID::TRG_WIDTH).as_int() != 0)
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sync_print_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
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sync_print_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
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else
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else
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schedule[module].push_back(*node);
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schedule[module].push_back(*node);
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