From 88ff2966573908873ff75c07ff3d40bb142ebba1 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Wed, 11 Dec 2024 11:04:35 -0800 Subject: [PATCH 1/2] Activity info and rename cmd --- Makefile | 2 +- passes/sat/sim.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index fd8af46e5..a241bd51c 100644 --- a/Makefile +++ b/Makefile @@ -759,7 +759,7 @@ OBJS += passes/cmds/reconstructbusses.o OBJS += passes/cmds/longloop_select.o OBJS += passes/sat/sim.o OBJS += passes/techmap/bufnorm.o - +OBJS += passes/cmds/rename.o OBJS += passes/cmds/segv.o include $(YOSYS_SRC)/passes/hierarchy/Makefile.inc diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index ebf002c46..062ba2579 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2440,7 +2440,7 @@ struct AnnotateActivity : public OutputWriter { } } } - log("Computing signal activity for %ld signals (%d bits)", use_signal.size(), nbTotalBits); + log("Computing signal activity for %ld signals (%d bits)\n", use_signal.size(), nbTotalBits); log_flush(); // Max simulation time int max_time = 0; From fc63cd7f585f5cdc0713f92597d953c0083fb43a Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Wed, 11 Dec 2024 11:04:53 -0800 Subject: [PATCH 2/2] Activity info and rename cmd --- passes/cmds/activity.cc | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/passes/cmds/activity.cc b/passes/cmds/activity.cc index 2ebf513d0..e69edd75a 100644 --- a/passes/cmds/activity.cc +++ b/passes/cmds/activity.cc @@ -28,6 +28,7 @@ struct ActivityProp { Module *module; SigMap sigmap; uint32_t nbBitsWithActivity = 0; + uint32_t wireCount = 0; // Split a string based on separator, returns a vector of tokens as reference argument // If skipEmpty is true, return "" for string " ", when separator is " " @@ -66,7 +67,14 @@ struct ActivityProp { std::map ActivityMap; std::map DutyMap; // Build {signal bit - activity} map from the wire activities calculated in the sim pass + + bool debug = false; + if (std::getenv("DEBUG_ACTIVITY_PROP")) { + debug = true; + } + int localActivity = 0; for (Wire *wire : module->wires()) { + wireCount++; SigSpec sig(sigmap(wire)); // Retrieve the activity/dutycycle attributes created in the sim pass, attached to wires, in the form: // $ACKT: 0.1 0.2 .... (Each bit in a bus has its own activity, index 0 of the bus is left most) @@ -83,14 +91,20 @@ struct ActivityProp { ActivityMap.emplace(bit, activities[i]); DutyMap.emplace(bit, duties[i]); nbBitsWithActivity++; + localActivity++; + if (debug) + log("Found activity for module: %s, wire: %s, wire_size: %d, activity: %s\n", module->name.c_str(), wire->name.c_str(), GetSize(sig), act.c_str()); } else { - log_warning("Zeroing out activity for module: %s, wire: %s, wire_size: %d, activ_size: %ld\n", - module->name.c_str(), wire->name.c_str(), GetSize(sig), activities.size()); + if (debug) + log_warning("Zeroing out activity for module: %s, wire: %s, wire_size: %d, activ_size: %ld\n", + module->name.c_str(), wire->name.c_str(), GetSize(sig), activities.size()); ActivityMap.emplace(bit, "0.0"); DutyMap.emplace(bit, "0.0"); } } } + if (localActivity) + log("Collected %d bits with activity in module %s out of %d wires\n", localActivity, module->name.c_str(), wireCount); // Attach port activity to cell using sigmap for (auto cell : module->cells()) { std::string cell_ports_activity; @@ -136,6 +150,7 @@ struct ActivityProp { } uint32_t getNbBitsWithActivity() { return nbBitsWithActivity; } + uint32_t getWireCount() { return wireCount; } }; struct ActivityClear { @@ -174,11 +189,13 @@ struct ActivityPropPass : public Pass { } extra_args(args, argidx, design); uint32_t totalNbBitsWithActivity = 0; - for (auto module : design->modules()) { + uint32_t wireCount = 0; + for (auto module : design->selected_modules()) { ActivityProp worker(module); totalNbBitsWithActivity += worker.getNbBitsWithActivity(); + wireCount += worker.getWireCount(); } - log("Collected %d bits with activity\n", totalNbBitsWithActivity); + log("Collected %d bits in total with activity out of %d wires\n", totalNbBitsWithActivity, wireCount); log_flush(); } } ActivityPropPass; @@ -203,7 +220,7 @@ struct ActivityClearPass : public Pass { } extra_args(args, argidx, design); - for (auto module : design->modules()) { + for (auto module : design->selected_modules()) { ActivityClear worker(module); } }