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Merge pull request #988 from YosysHQ/clifford/fix987

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Add approximate support for SV "var" keyword
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Clifford Wolf 2019-05-04 21:58:25 +02:00 • committed by GitHub
commit 70d0f389ad
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2 changed files with 5 additions and 1 deletions
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frontends/verilog/verilog_lexer.l
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@ -208,6 +208,7 @@ YOSYS_NAMESPACE_END
"endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
"final" { SV_KEYWORD(TOK_FINAL); }
"logic" { SV_KEYWORD(TOK_LOGIC); }
"var" { SV_KEYWORD(TOK_VAR); }
"bit" { SV_KEYWORD(TOK_REG); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }