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Add tests for implicit wires in generate blocks.

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Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
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Yannick Lamarre 2024-02-23 21:33:14 -05:00 • committed by Emil J. Tywoniak
parent 109abd3224
commit 702e1f2467
2 changed files with 36 additions and 0 deletions
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tests/verilog/genblk_wire.sv Normal file
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module gold(a, b);
output wire [1:0] a;
input wire [1:0] b;
genvar i;
for (i = 0; i < 2; i++) begin
wire x;
assign x = b[i];
assign a[i] = x;
end
endmodule
module gate(a, b);
output wire [1:0] a;
input wire [1:0] b;
genvar i;
for (i = 0; i < 2; i++) begin
assign x = b[i];
assign a[i] = x;
end
endmodule