mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-07 06:33:24 +00:00
Code Activity

read_verilog: fix -1 constant used to correct post increment/decrement

Browse source
This commit is contained in:
George Rennie 2025-05-30 14:25:35 +01:00
parent 4f7ea38b49
commit 70291f0e49
1 changed files with 2 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
frontends/verilog/verilog_parser.y
View file

@ -336,7 +336,8 @@ static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AS
log_assert(stmt->type == AST_ASSIGN_EQ); log_assert(stmt->type == AST_ASSIGN_EQ);
AstNode *expr = stmt->children[0]->clone(); AstNode *expr = stmt->children[0]->clone();
if (undo) { if (undo) {
AstNode *minus_one = AstNode::mkconst_int(-1, true, 1); AstNode *one = AstNode::mkconst_int(1, false, 1);
AstNode *minus_one = new AstNode(AST_NEG, one);
expr = new AstNode(op, expr, minus_one); expr = new AstNode(op, expr, minus_one);
} }
SET_AST_NODE_LOC(expr, begin, end); SET_AST_NODE_LOC(expr, begin, end);