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equiv_purge bugfix, using SigChunk in Yosys namespace

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This commit is contained in:
Clifford Wolf 2015-10-24 19:09:45 +02:00
parent 2a0f577f83
commit 6fe48cf41e
5 changed files with 8 additions and 5 deletions
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2
passes/techmap/extract.cc
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@ -737,7 +737,7 @@ struct ExtractPass : public Pass {
RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections()) {
std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
std::vector<SigChunk> chunks = sigmap(conn.second);
for (auto &chunk : chunks)
if (chunk.wire != NULL)
chunk.wire = newMod->wires_.at(chunk.wire->name);

2
passes/techmap/techmap.cc
View file

@ -49,7 +49,7 @@ void apply_prefix(std::string prefix, std::string &id)
void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{
std::vector<RTLIL::SigChunk> chunks = sig;
vector<SigChunk> chunks = sig;
for (auto &chunk : chunks)
if (chunk.wire != NULL) {
std::string wire_name = chunk.wire->name.str();