Merge remote-tracking branch 'origin/main' into gussmith23-rosette-backend-updates

tests/.gitignore

@@ -1,2 +1,4 @@
 *.log
+*.out
+*.err
 run-test.mk

tests/aiger/.gitignore

@@ -1,3 +1,2 @@
 /*_ref.v
-/*.log
 /neg.out/

tests/aiger/io.ys

@@ -0,0 +1,10 @@
+read_verilog <<EOF
+module bad(
+	input in,
+	output reg [1:0] out
+);
+	assign out = {in, 1'b0};
+endmodule
+EOF
+proc
+write_aiger -vmap /dev/null /dev/null

tests/arch/anlogic/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/anlogic/mux.ys

@@ -36,9 +36,17 @@ select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 5 t:AL_MAP_LUT6
 
-select -assert-none t:AL_MAP_LUT6 %% t:* %D
+# Flaky test, started failing with statically allocated IdStrings, but works
+# for me locally when I scramble the names using:
+#
+#     rename -scramble-name -seed 1
+#
+
+#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+#cd mux16 # Constrain all select calls below inside the top module
+#show
+#select -assert-count 5 t:AL_MAP_LUT6
+
+#select -assert-none t:AL_MAP_LUT6 %% t:* %D

tests/arch/ecp5/.gitignore

@@ -1,2 +0,0 @@
-*.log
-/run-test.mk

tests/arch/efinix/.gitignore

@@ -1,3 +0,0 @@
-/*.log
-/*.out
-/run-test.mk

tests/arch/fabulous/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/gatemate/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/gowin/.gitignore

@@ -1,3 +0,0 @@
-/*.log
-/*.out
-/run-test.mk

tests/arch/gowin/mux.ys

@@ -32,8 +32,8 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT1
-select -assert-count 10 t:LUT3
+select -assert-count 3 t:LUT1
+select -assert-count 2 t:LUT3
 select -assert-count 1 t:LUT4
 select -assert-count 5 t:MUX2_LUT5
 select -assert-count 2 t:MUX2_LUT6

tests/arch/ice40/.gitignore

@@ -1,5 +1,3 @@
-*.log
 *.json
-/run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/intel_alm/.gitignore

@@ -1,2 +0,0 @@
-/*.log
-/run-test.mk

tests/arch/machxo2/.gitignore

@@ -1,2 +0,0 @@
-*.log
-/run-test.mk

tests/arch/microchip/.gitignore

@@ -1,4 +1,2 @@
-*.log
-/run-test.mk
 *.vm
 

tests/arch/nanoxplore/.gitignore

@@ -1,2 +0,0 @@
-*.log
-/run-test.mk

tests/arch/nexus/.gitignore

@@ -1,2 +0,0 @@
-/*.log
-/run-test.mk

tests/arch/quicklogic/.gitignore

@@ -1,4 +1,2 @@
-*.log
-run-test.mk
 +*_synth.v
 +*_testbench

tests/arch/quicklogic/pp3/fsm.ys

@@ -11,8 +11,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:LUT2
-select -assert-count 9 t:LUT3
 select -assert-count 4 t:dffepc
 select -assert-count 1 t:logic_0
 select -assert-count 1 t:logic_1
@@ -20,4 +18,4 @@ select -assert-count 3 t:inpad
 select -assert-count 2 t:outpad
 select -assert-count 1 t:ckpad
 
-select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D

tests/arch/xilinx/.gitignore

@@ -1,5 +1,3 @@
-/*.log
-/*.out
 /run-test.mk
 /*_uut.v
 /test_macc

tests/arch/xilinx/dsp_cascade.ys

@@ -69,7 +69,8 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 design -load postopt
 cd cascade
 select -assert-count 2 t:DSP48E1
-select -assert-none t:DSP48E1 t:BUFG %% t:* %D
+# TODO Disabled check, FDREs emitted due to order sensitivity
+# select -assert-none t:DSP48E1 t:BUFG %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)
 select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i

tests/asicworld/.gitignore

@@ -1,2 +0,0 @@
-*.log
-*.out

tests/bind/.gitignore

@@ -1,2 +0,0 @@
-*.log
-run-test.mk

tests/blif/.gitignore

@@ -1 +0,0 @@
-*.log

tests/bugpoint/.gitignore

@@ -0,0 +1,5 @@
+bugpoint-case.*
+*.log
+*.err
+*.temp
+run-test.mk

tests/bugpoint/failures.ys

@@ -0,0 +1,29 @@
+write_file fail.temp << EOF
+logger -expect error "Missing -script or -command option." 1
+bugpoint -suffix fail -yosys ../../yosys
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "do not crash on this design" 1
+bugpoint -suffix fail -yosys ../../yosys -command "dump"
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "returned value 3 instead of expected 7" 1
+bugpoint -suffix fail -yosys ../../yosys -command raise_error -expect-return 7
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "not found in the log file!" 1
+bugpoint -suffix fail -yosys ../../yosys -command raise_error -grep "nope"
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
+
+write_file fail.temp << EOF
+logger -expect error "not found in stderr log!" 1
+bugpoint -suffix fail -yosys ../../yosys -command raise_error -err-grep "nope"
+EOF
+exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp

tests/bugpoint/mod_constraints.ys

@@ -0,0 +1,83 @@
+read_rtlil mods.il
+select -assert-count 7 w:*
+select -assert-mod-count 3 =*
+select -assert-count 4 c:*
+design -stash base
+
+# everything is removed by default
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# don't remove wires
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -modules -cells
+select -assert-count 3 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# don't remove cells or their connections
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules
+select -assert-count 5 w:*
+select -assert-mod-count 1 =*
+select -assert-count 4 c:*
+
+# don't remove cells but do remove their connections
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules -connections
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-count 4 c:*
+
+# don't remove modules
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -cells
+select -assert-count 1 w:*
+select -assert-mod-count 3 =*
+select -assert-none c:*
+
+# can keep wires
+design -load base
+setattr -set bugpoint_keep 1 w:w_b
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 2 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# a wire with keep won't keep the cell/module containing it
+design -load base
+setattr -set bugpoint_keep 1 w:w_o
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-none c:*
+
+# can keep cells (and do it without the associated module)
+design -load base
+setattr -set bugpoint_keep 1 c:c_a
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 1 =*
+select -assert-count 1 c:*
+
+# can keep modules
+design -load base
+setattr -mod -set bugpoint_keep 1 m_a
+bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
+select -assert-count 1 w:*
+select -assert-mod-count 2 =*
+select -assert-none c:*
+
+# minimize to just the path connecting w_a and w_c
+# which happens via w_b, w_i, w_o, m_a, c_a and c_b
+write_file script.temp << EOF
+select -assert-none w:w_a %co* w:w_c %ci* %i
+EOF
+design -load base
+bugpoint -suffix mods -yosys ../../yosys -script script.temp -grep "Assertion failed"
+select -assert-count 5 w:*
+select -assert-mod-count 2 =*
+select -assert-count 2 c:*

tests/bugpoint/mods.il

@@ -0,0 +1,38 @@
+module \m_a
+    wire input 1 \w_i
+    wire output 2 \w_o
+    connect \w_o \w_i
+end
+
+module \m_b
+    wire input 1 \w_i
+    wire output 2 \w_o
+end
+
+attribute \top 1
+module \top
+    attribute \raise_error 3
+    wire \w_a
+    wire \w_b
+    wire \w_c
+
+    cell \m_a \c_a
+        connect \w_i \w_a
+        connect \w_o \w_b
+    end
+
+    cell \m_a \c_b
+        connect \w_i \w_b
+        connect \w_o \w_c
+    end
+
+    cell \m_b \c_c
+        connect \w_i \w_c
+        connect \w_o \w_a
+    end
+
+    cell \m_b \c_d
+        connect \w_i 1'0
+        connect \w_o 1'1
+    end
+end

tests/bugpoint/proc_constraints.ys

@@ -0,0 +1,49 @@
+read_rtlil procs.il
+select -assert-count 2 p:*
+design -stash err_q
+
+# processes get removed by default
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
+select -assert-none p:*
+
+# individual processes can be kept
+design -load err_q
+setattr -set bugpoint_keep 1 p:proc_a
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
+select -assert-count 1 p:*
+
+# all processes can be kept
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -wires
+select -assert-count 2 p:*
+
+# d and clock are connected after proc
+design -load err_q
+proc
+select -assert-count 3 w:d %co
+select -assert-count 3 w:clock %co
+
+# no assigns means no d
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -assigns
+proc
+select -assert-count 1 w:d %co
+
+# no updates means no clock
+design -load err_q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -updates
+proc
+select -assert-count 1 w:clock %co
+
+# can remove ports
+design -load err_q
+select -assert-count 5 x:*
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
+select -assert-none x:*
+
+# can keep ports
+design -load err_q
+setattr -set bugpoint_keep 1 i:d o:q
+bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
+select -assert-count 2 x:*

tests/bugpoint/procs.il

@@ -0,0 +1,42 @@
+module \ff_with_en_and_sync_reset
+  wire $0\q[1:1]
+  wire $0\q[0:0]
+  attribute \raise_error 4
+  wire width 2 output 5 \q
+  wire width 2 input 4 \d
+  wire input 3 \enable
+  wire input 2 \reset
+  wire input 1 \clock
+
+  process \proc_a
+    assign $0\q[0:0] \q [0]
+    switch \reset
+      case 1'1
+        assign $0\q[0:0] 1'0
+      case 
+        switch \enable
+          case 1'1
+            assign $0\q[0:0] \d [0]
+          case 
+        end
+    end
+    sync posedge \clock
+      update \q [0] $0\q[0:0]
+  end
+
+  process \proc_b
+    assign $0\q[1:1] \q [1]
+    switch \reset
+      case 1'1
+        assign $0\q[1:1] 1'0
+      case 
+        switch \enable
+          case 1'1
+            assign $0\q[1:1] \d [1]
+          case 
+        end
+    end
+    sync posedge \clock
+      update \q [1] $0\q[1:1]
+  end
+end

tests/bugpoint/raise_error.ys

@@ -0,0 +1,63 @@
+read_verilog -noblackbox << EOF
+(* raise_error=7 *)
+module top();
+endmodule
+
+(* raise_error="help me" *)
+module other();
+endmodule
+
+(* raise_error *)
+module def();
+endmodule
+EOF
+select -assert-mod-count 3 =*
+design -stash read
+
+# empty design does not raise_error
+design -reset
+logger -expect log "'raise_error' attribute not found" 1
+raise_error
+logger -check-expected
+
+# raise_error with int exits with status
+design -load read
+setattr -mod -unset raise_error def other
+dump
+bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 top
+
+# raise_error -always still uses 'raise_error' attribute if possible
+design -load read
+setattr -mod -unset raise_error def other
+bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 top
+
+# raise_error with string prints message and exits with 1
+design -load read
+setattr -mod -unset raise_error top def
+bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 other
+
+# raise_error with no value exits with 1
+design -load read
+setattr -mod -unset raise_error top
+delete other
+bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 def
+
+# raise_error -stderr prints to stderr and exits with 1
+design -load read
+setattr -mod -unset raise_error top def
+bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1
+select -assert-mod-count 1 =*
+select -assert-mod-count 1 other
+
+# empty design can raise_error -always
+design -reset
+bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -grep "ERROR: No 'raise_error' attribute found" -expect-return 1
+bugpoint -suffix error -yosys ../../yosys -command "raise_error -always -stderr" -err-grep "No 'raise_error' attribute found" -expect-return 1

tests/bugpoint/run-test.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+generate_mk --yosys-scripts

tests/cxxrtl/run-test.sh

@@ -5,7 +5,7 @@ set -ex
 run_subtest () {
     local subtest=$1; shift
 
-    ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++
+    ${CXX:-g++} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++
     ./cxxrtl-test-${subtest}
 }
 
@@ -14,4 +14,4 @@ run_subtest value_fuzz
 
 # Compile-only test.
 ../../yosys -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
-${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
+${CXX:-g++} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc

tests/fmt/.gitignore

@@ -1,3 +1,2 @@
-*.log
 iverilog-*
 yosys-*

tests/fmt/run-test.sh

@@ -51,7 +51,7 @@ test_cxxrtl () {
 	local subtest=$1; shift
 
 	../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc"
-	${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
+	${CXX:-g++} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
 	./yosys-${subtest} 2>yosys-${subtest}.log
 	iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v
 	./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log
@@ -69,7 +69,7 @@ diff iverilog-always_full.log iverilog-always_full-1.log
 
 ../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log
 ../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc"
-${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
+${CXX:-g++} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
 ./yosys-display_lm_cc >yosys-display_lm_cc.log
 for log in yosys-display_lm.log yosys-display_lm_cc.log; do
 	grep "^%l: \\\\bot\$" "$log"

tests/functional/test_functional.py

@@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args):
     run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
 
 def yosys_synth(verilog_file, rtlil_file):
-    yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}")
+    yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven -undef ; write_rtlil {quote(rtlil_file)}")
 
 # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
 def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
@@ -93,4 +93,4 @@ def test_print_graph(tmp_path):
     tb_file = base_path / 'tests/functional/picorv32_tb.v'
     cpu_file = base_path / 'tests/functional/picorv32.v'
     # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl
-    yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic")
+    yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven -undef ; flatten; clk2fflogic; test_generic")

tests/hana/.gitignore

@@ -1,2 +0,0 @@
-*.log
-*.out

tests/liberty/.gitignore

@@ -1,3 +1,2 @@
-*.log
 /*.filtered
 *.verilogsim

tests/liberty/XNOR2X1.lib.verilogsim.ok

@@ -2,5 +2,5 @@ module XNOR2X1 (B, A, Y);
   input B;
   input A;
   output Y;
-  assign Y = !(B&!A|!B&A); // "!(B&!A|!B&A)"
+  assign Y = (~((B&(~A))|((~B)&A))); // "!(B&!A|!B&A)"
 endmodule

tests/liberty/dff.lib

@@ -5,7 +5,7 @@ library(dff) {
     area : 1;
     ff("IQ", "IQN") {
       next_state : "(D)";
-      clocked_on : "CLK";
+      clocked_on : (CLK);
     } 
     pin(D) {
       direction : input;
@@ -15,7 +15,7 @@ library(dff) {
     }
     pin(Q) {
       direction: output;
-      function : "IQ";   
+      function : IQ;   
     }
   }
 

tests/liberty/dff.lib.filtered.ok

@@ -3,7 +3,7 @@ library(dff) {
     area : 1 ;
     ff("IQ", "IQN") {
       next_state : "(D)" ;
-      clocked_on : "CLK" ;
+      clocked_on :  ( CLK ) ;
     }
     pin(D) {
       direction : input ;
@@ -13,7 +13,7 @@ library(dff) {
     }
     pin(Q) {
       direction : output ;
-      function : "IQ" ;
+      function : IQ ;
     }
   }
 }

tests/liberty/dff.lib.verilogsim.ok

@@ -1,12 +1,12 @@
 module dff (D, CLK, Q);
-  reg "IQ", "IQN";
+  reg IQ, IQN;
   input D;
   input CLK;
   output Q;
-  assign Q = IQ; // "IQ"
+  assign Q = IQ; // IQ
   always @(posedge CLK) begin
       // "(D)"
-      "IQ" <= (D);
-      "IQN" <= ~((D));
+      IQ <= D;
+      IQN <= ~(D);
   end
 endmodule

tests/liberty/libcache.ys

@@ -1,4 +1,5 @@
-libcache -enable busdef.lib
+libcache -verbose
+libcache -enable bus*f.lib
 
 logger -expect log "Caching is disabled by default." 1
 logger -expect log "Caching is enabled for `busdef.lib'." 1
@@ -14,8 +15,8 @@ logger -expect log "Caching data" 1
 read_liberty -lib busdef.lib; design -reset
 logger -check-expected
 
-logger -expect log "Using caching data" 1
-log Using caching data
+logger -expect log "Using cached data" 1
+log Using cached data
 read_liberty normal.lib; design -reset
 logger -check-expected
 
@@ -23,6 +24,13 @@ logger -expect log "Using cached data" 1
 read_liberty -lib busdef.lib; design -reset
 logger -check-expected
 
+libcache -quiet
+logger -expect log "Using cached data" 1
+log Using cached data
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+libcache -verbose
+
 libcache -purge busdef.lib
 
 logger -expect log "Caching is disabled by default." 1

tests/liberty/normal.lib.verilogsim.ok

@@ -1,13 +1,13 @@
 module inv (A, Y);
   input A;
   output Y;
-  assign Y = ~A; // "A'"
+  assign Y = (~A); // "A'"
 endmodule
 module tri_inv (A, S, Z);
   input A;
   input S;
   output Z;
-  assign Z = ~A; // "A'"
+  assign Z = (~A); // "A'"
 endmodule
 module buffer (A, Y);
   input A;
@@ -18,29 +18,29 @@ module nand2 (A, B, Y);
   input A;
   input B;
   output Y;
-  assign Y = ~(A&B); // "(A * B)'"
+  assign Y = (~(A&B)); // "(A * B)'"
 endmodule
 module nor2 (A, B, Y);
   input A;
   input B;
   output Y;
-  assign Y = ~(A|B); // "(A + B)'"
+  assign Y = (~(A|B)); // "(A + B)'"
 endmodule
 module xor2 (A, B, Y);
   input A;
   input B;
   output Y;
-  assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
+  assign Y = ((A&(~B))|((~A)&B)); // "(A *B') + (A' * B)"
 endmodule
 module imux2 (A, B, S, Y);
   input A;
   input B;
   input S;
   output Y;
-  assign Y = ~(&(A&S)|(B&~S)&); // "( (A * S) + (B * S') )'"
+  assign Y = (~((A&S)|(B&(~S)))); // "( (A * S) + (B * S') )'"
 endmodule
 module dff (D, CLK, RESET, PRESET, Q, QN);
-  reg "IQ", "IQN";
+  reg IQ, IQN;
   input D;
   input CLK;
   input RESET;
@@ -51,26 +51,26 @@ module dff (D, CLK, RESET, PRESET, Q, QN);
   assign QN = IQN; // "IQN"
   always @(posedge CLK, posedge RESET, posedge PRESET) begin
     if ((RESET) && (PRESET)) begin
-      "IQ" <= 0;
-      "IQN" <= 0;
+      IQ <= 0;
+      IQN <= 0;
     end
     else if (RESET) begin
-      "IQ" <= 0;
-      "IQN" <= 1;
+      IQ <= 0;
+      IQN <= 1;
     end
     else if (PRESET) begin
-      "IQ" <= 1;
-      "IQN" <= 0;
+      IQ <= 1;
+      IQN <= 0;
     end
     else begin
       // "D"
-      "IQ" <= D;
-      "IQN" <= ~(D);
+      IQ <= D;
+      IQN <= ~(D);
     end
   end
 endmodule
 module latch (D, G, Q, QN);
-  reg "IQ", "IQN";
+  reg IQ, IQN;
   input D;
   input G;
   output Q;
@@ -79,8 +79,8 @@ module latch (D, G, Q, QN);
   assign QN = IQN; // "IQN"
   always @* begin
     if (G) begin
-      "IQ" <= D;
-      "IQN" <= ~(D);
+      IQ <= D;
+      IQN <= ~(D);
     end
   end
 endmodule
@@ -89,14 +89,14 @@ module aoi211 (A, B, C, Y);
   input B;
   input C;
   output Y;
-  assign Y = ~((A&B)|C); // "((A * B) + C)'"
+  assign Y = (~((A&B)|C)); // "((A * B) + C)'"
 endmodule
 module oai211 (A, B, C, Y);
   input A;
   input B;
   input C;
   output Y;
-  assign Y = ~((A|B)&C); // "((A + B) * C)'"
+  assign Y = (~((A|B)&C)); // "((A + B) * C)'"
 endmodule
 module halfadder (A, B, C, Y);
   input A;
@@ -104,7 +104,7 @@ module halfadder (A, B, C, Y);
   output C;
   assign C = (A&B); // "(A * B)"
   output Y;
-  assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
+  assign Y = ((A&(~B))|((~A)&B)); // "(A *B') + (A' * B)"
 endmodule
 module fulladder (A, B, CI, CO, Y);
   input A;

tests/liberty/unquoted.lib

@@ -0,0 +1,60 @@
+library(dff_unquoted) {
+  cell (dff1) {
+    area : 1;
+    ff("IQ", "IQN") {
+      next_state : !D;
+      clocked_on : (CLK);
+    }
+    pin(D) {
+      direction : input;
+    }
+    pin(CLK) {
+      direction : input;
+    }
+    pin(Q) {
+      direction: output;
+      function : IQ;
+    }
+  }
+  cell (dff2) {
+    area : 1;
+    ff(IQ, IQN) {
+      next_state : D';
+      clocked_on : CLK;
+    }
+    pin(D) {
+      direction : input;
+    }
+    pin(CLK) {
+      direction : input;
+    }
+    pin(Q) {
+      direction: output;
+      function : "IQ";
+    }
+  }
+  cell (dffe) {
+    area : 6;
+    ff("IQ", "IQN") {
+      next_state : (D&EN) | (IQ&!EN);
+      clocked_on : !CLK;
+    }
+    pin(D) {
+      direction : input;
+    }
+    pin(EN) {
+      direction : input;
+    }
+    pin(CLK) {
+      direction : input;
+    }
+    pin(Q) {
+      direction: output;
+      function : "IQ";
+    }
+    pin(QN) {
+      direction: output;
+      function : "IQN";
+    }
+  }
+}

tests/liberty/unquoted.lib.filtered.ok

@@ -0,0 +1,60 @@
+library(dff_unquoted) {
+  cell(dff1) {
+    area : 1 ;
+    ff("IQ", "IQN") {
+      next_state : !D ;
+      clocked_on :  ( CLK ) ;
+    }
+    pin(D) {
+      direction : input ;
+    }
+    pin(CLK) {
+      direction : input ;
+    }
+    pin(Q) {
+      direction : output ;
+      function : IQ ;
+    }
+  }
+  cell(dff2) {
+    area : 1 ;
+    ff(IQ, IQN) {
+      next_state : D ' ;
+      clocked_on : CLK ;
+    }
+    pin(D) {
+      direction : input ;
+    }
+    pin(CLK) {
+      direction : input ;
+    }
+    pin(Q) {
+      direction : output ;
+      function : "IQ" ;
+    }
+  }
+  cell(dffe) {
+    area : 6 ;
+    ff("IQ", "IQN") {
+      next_state :  ( D & EN ) | ( IQ & ! EN ) ;
+      clocked_on : !CLK ;
+    }
+    pin(D) {
+      direction : input ;
+    }
+    pin(EN) {
+      direction : input ;
+    }
+    pin(CLK) {
+      direction : input ;
+    }
+    pin(Q) {
+      direction : output ;
+      function : "IQ" ;
+    }
+    pin(QN) {
+      direction : output ;
+      function : "IQN" ;
+    }
+  }
+}

tests/liberty/unquoted.lib.verilogsim.ok

@@ -0,0 +1,39 @@
+module dff1 (D, CLK, Q);
+  reg IQ, IQN;
+  input D;
+  input CLK;
+  output Q;
+  assign Q = IQ; // IQ
+  always @(posedge CLK) begin
+      // !D
+      IQ <= (~D);
+      IQN <= ~((~D));
+  end
+endmodule
+module dff2 (D, CLK, Q);
+  reg IQ, IQN;
+  input D;
+  input CLK;
+  output Q;
+  assign Q = IQ; // "IQ"
+  always @(posedge CLK) begin
+      // D '
+      IQ <= (~D);
+      IQN <= ~((~D));
+  end
+endmodule
+module dffe (D, EN, CLK, Q, QN);
+  reg IQ, IQN;
+  input D;
+  input EN;
+  input CLK;
+  output Q;
+  assign Q = IQ; // "IQ"
+  output QN;
+  assign QN = IQN; // "IQN"
+  always @(negedge CLK) begin
+      //  ( D & EN ) | ( IQ & ! EN )
+      IQ <= ((D&EN)|(IQ&(~EN)));
+      IQN <= ~(((D&EN)|(IQ&(~EN))));
+  end
+endmodule

tests/lut/.gitignore

@@ -1 +0,0 @@
-*.log

tests/memlib/.gitignore

@@ -1,5 +1,2 @@
-t_*.log
-t_*.out
 t_*.v
 t_*.ys
-run-test.mk

tests/memories/.gitignore

@@ -1,3 +1 @@
-*.log
-*.out
 *.dmp

tests/opt/alumacc.ys

@@ -0,0 +1,33 @@
+read_verilog <<EOT
+module top(...);
+
+input [7:0] ra;
+input [7:0] rb;
+output gt;
+output sgt;
+output lt;
+output slt;
+
+output ge;
+output eq;
+output seq;
+output ne;
+
+assign gt = ra > rb;
+assign sgt = $signed(ra) > $signed(rb);
+assign lt = ra < rb;
+assign slt = $signed(ra) < $signed(rb);
+
+assign ge = ra >= rb;
+assign eq = ra == rb;
+assign seq = $signed(ra) == $signed(rb);
+assign ne = ra != rb;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt -assert alumacc
+alumacc
+select -assert-count 1 t:$alu

tests/opt/bug5164.ys

@@ -0,0 +1,60 @@
+read_rtlil <<EOT
+module \module137
+  wire input 1 \clk
+  wire width 1 output 1 \qa
+  wire width 1 \qb
+  cell $dff \dffa
+    parameter \CLK_POLARITY 1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D \qb
+    connect \Q \qa
+  end
+  cell $dff \dffb
+    parameter \CLK_POLARITY 1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D 1'x
+    connect \Q \qb
+  end
+end
+EOT
+equiv_opt -assert opt_dff -sat
+
+design -reset
+
+read_rtlil <<EOT
+module \module137
+  wire output 1 width 9 $2\reg204[8:0]
+  wire input 1 \clk
+  wire width 9 $auto$wreduce.cc:514:run$19340
+  wire width 9 $auto$wreduce.cc:514:run$19341
+  wire width 15 \dffout
+  attribute \init 9'000000000
+  wire width 9 \reg204
+  cell $dff $auto$ff.cc:266:slice$26225
+    parameter \CLK_POLARITY 1
+    parameter \WIDTH 15
+    connect \CLK \clk
+    connect \D { 9'x \reg204 [8:3] }
+    connect \Q \dffout
+  end
+  cell $dff $auto$ff.cc:266:slice$26292
+    parameter \CLK_POLARITY 1
+    parameter \WIDTH 9
+    connect \CLK \clk
+    connect \D $2\reg204[8:0]
+    connect \Q \reg204
+  end
+  cell $mux $procmux$4510
+    parameter \WIDTH 9
+    connect \A 9'x
+    connect \B 9'x
+    connect \S 1'x
+    connect \Y $auto$wreduce.cc:514:run$19340
+  end
+  connect $2\reg204[8:0] $auto$wreduce.cc:514:run$19340
+  connect $auto$wreduce.cc:514:run$19341 [8:3] 6'000000
+end
+EOT
+equiv_opt -assert opt_dff -sat

tests/opt/bug5398.ys

@@ -0,0 +1,23 @@
+read_verilog <<EOF
+module tag_2x4(
+  input        R0_clk,
+  input        W0_clk,
+  output       x,
+);
+  assign x = !W0_clk;
+endmodule
+
+module top(input clock, output x, output flag);
+  tag_2x4 tag_ext(
+    .R0_clk  (clock),
+    .W0_clk  (clock),
+    .x       (x)
+  );
+  assign flag = x ^ clock;
+endmodule
+EOF
+
+hierarchy -top top
+opt_hier
+flatten
+sat -verify -prove flag 1

tests/opt/opt_dff-simplify.il

@@ -0,0 +1,648 @@
+# Generated by Yosys 0.53+24 (git sha1 ab636979e, sccache clang++ 19.1.7 -fPIC -O3 -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=address,undefined)
+autoidx 171528
+attribute \hdlname "csr_regfile_0000000000000000_1"
+module \csr_regfile_0000000000000000_1
+  wire $delete_wire$169641
+  wire $delete_wire$169642
+  wire $delete_wire$169643
+  wire $delete_wire$169644
+  wire $delete_wire$169645
+  wire $delete_wire$169646
+  wire $delete_wire$169647
+  wire $delete_wire$169648
+  wire $delete_wire$169649
+  wire $delete_wire$169650
+  wire $delete_wire$169651
+  wire $delete_wire$169652
+  wire $delete_wire$169653
+  wire $delete_wire$169654
+  wire $delete_wire$169655
+  wire $delete_wire$169656
+  wire $delete_wire$169657
+  wire $delete_wire$169658
+  wire $delete_wire$169659
+  wire $delete_wire$169660
+  wire $delete_wire$169661
+  wire $delete_wire$169662
+  wire $delete_wire$169663
+  wire $delete_wire$169664
+  wire $delete_wire$169665
+  wire $delete_wire$169666
+  wire $delete_wire$169667
+  wire $delete_wire$169668
+  wire $delete_wire$169669
+  wire $delete_wire$169670
+  wire $delete_wire$169671
+  wire $delete_wire$169672
+  wire $delete_wire$169673
+  wire $delete_wire$169674
+  wire $delete_wire$169675
+  wire $delete_wire$169676
+  wire $delete_wire$169677
+  wire $delete_wire$169678
+  wire $delete_wire$169679
+  wire $delete_wire$169680
+  wire $delete_wire$169681
+  wire $delete_wire$169682
+  wire $delete_wire$169683
+  wire $delete_wire$169684
+  wire $delete_wire$169685
+  wire $delete_wire$169686
+  wire $delete_wire$169687
+  wire $delete_wire$169688
+  wire $delete_wire$169689
+  wire $delete_wire$169690
+  wire $delete_wire$169691
+  wire $delete_wire$169692
+  wire $delete_wire$169693
+  wire $delete_wire$169694
+  wire $delete_wire$169695
+  wire $delete_wire$169696
+  wire $delete_wire$169697
+  wire $delete_wire$169698
+  wire $delete_wire$169699
+  wire $delete_wire$169700
+  wire $delete_wire$169701
+  wire $delete_wire$169702
+  wire $delete_wire$169703
+  wire $delete_wire$169704
+  wire $delete_wire$169705
+  wire $delete_wire$169706
+  wire $delete_wire$169707
+  wire $delete_wire$169708
+  wire $delete_wire$169709
+  wire $delete_wire$169710
+  wire $delete_wire$169711
+  wire $delete_wire$169712
+  wire width 32 $delete_wire$169713
+  wire $delete_wire$169714
+  wire $delete_wire$169715
+  wire $delete_wire$169716
+  wire $delete_wire$169717
+  wire $delete_wire$169718
+  wire $delete_wire$169719
+  wire $delete_wire$169720
+  wire $delete_wire$169721
+  wire $delete_wire$169722
+  wire $delete_wire$169723
+  wire $delete_wire$169724
+  wire $delete_wire$169725
+  wire $delete_wire$169726
+  wire $delete_wire$169727
+  wire $delete_wire$169728
+  wire $delete_wire$169729
+  wire $delete_wire$169730
+  wire $delete_wire$169731
+  wire $delete_wire$169732
+  wire $delete_wire$169733
+  wire $delete_wire$169734
+  wire $delete_wire$169735
+  wire $delete_wire$169736
+  wire $delete_wire$169737
+  wire $delete_wire$169738
+  wire $delete_wire$169739
+  wire $delete_wire$169740
+  wire $delete_wire$169741
+  wire $delete_wire$169742
+  wire $delete_wire$169743
+  wire $delete_wire$169744
+  wire $delete_wire$169745
+  wire $delete_wire$169746
+  wire $delete_wire$169747
+  wire $delete_wire$169748
+  wire $delete_wire$169749
+  wire $delete_wire$169750
+  wire $delete_wire$169751
+  wire $delete_wire$169752
+  wire $delete_wire$169753
+  wire $delete_wire$169754
+  wire $delete_wire$169755
+  wire $delete_wire$169756
+  wire $delete_wire$169757
+  wire $delete_wire$169758
+  wire $delete_wire$169759
+  wire $delete_wire$169760
+  wire $delete_wire$169761
+  wire $delete_wire$169762
+  wire $delete_wire$169763
+  wire $delete_wire$169764
+  wire $delete_wire$169765
+  wire $delete_wire$169766
+  wire $delete_wire$169767
+  wire $delete_wire$169768
+  wire $delete_wire$169769
+  wire $delete_wire$169770
+  wire $delete_wire$169771
+  wire $delete_wire$169772
+  wire $delete_wire$169773
+  wire $delete_wire$169774
+  wire $delete_wire$169775
+  wire $delete_wire$169776
+  wire $delete_wire$169777
+  wire $delete_wire$169778
+  wire $delete_wire$169779
+  wire $delete_wire$169780
+  wire $delete_wire$169781
+  wire $delete_wire$169782
+  wire $delete_wire$169783
+  wire $delete_wire$169784
+  wire $delete_wire$169785
+  wire $delete_wire$169786
+  wire $delete_wire$169787
+  wire $delete_wire$169788
+  wire $delete_wire$169789
+  wire $delete_wire$169790
+  wire $delete_wire$169791
+  wire $delete_wire$169792
+  wire $delete_wire$169793
+  wire $delete_wire$169794
+  wire $delete_wire$169795
+  wire $delete_wire$169796
+  wire $delete_wire$169797
+  wire $delete_wire$169798
+  wire $delete_wire$169799
+  wire $delete_wire$169800
+  wire $delete_wire$169801
+  wire $delete_wire$169802
+  wire $delete_wire$169803
+  wire $delete_wire$169804
+  wire $delete_wire$169805
+  wire $delete_wire$169806
+  wire $delete_wire$169807
+  wire $delete_wire$169808
+  wire $delete_wire$169809
+  wire $delete_wire$169810
+  wire $delete_wire$169811
+  wire $delete_wire$169812
+  wire $delete_wire$169813
+  wire $delete_wire$169814
+  wire $delete_wire$169815
+  wire $delete_wire$169816
+  wire $delete_wire$169817
+  wire $delete_wire$169818
+  wire $delete_wire$169819
+  wire $delete_wire$169820
+  wire $delete_wire$169821
+  wire width 5 $delete_wire$169822
+  wire width 17 $delete_wire$169823
+  wire $delete_wire$169824
+  wire $delete_wire$169825
+  wire $delete_wire$169826
+  wire $delete_wire$169827
+  wire $delete_wire$169828
+  wire $delete_wire$169829
+  wire $delete_wire$169830
+  wire $delete_wire$169831
+  wire $delete_wire$169832
+  wire $delete_wire$169833
+  wire $delete_wire$169834
+  wire $delete_wire$169835
+  wire $delete_wire$169836
+  wire $delete_wire$169837
+  wire $delete_wire$169838
+  wire $delete_wire$169839
+  wire $delete_wire$169840
+  wire $delete_wire$169960
+  wire $delete_wire$169961
+  wire $delete_wire$169962
+  wire $delete_wire$169963
+  wire $delete_wire$169964
+  wire $delete_wire$169965
+  wire $delete_wire$169966
+  wire $delete_wire$169967
+  wire $delete_wire$169968
+  wire $delete_wire$169969
+  wire $delete_wire$169970
+  wire $delete_wire$169971
+  wire $delete_wire$169972
+  wire $delete_wire$169973
+  wire $delete_wire$169974
+  wire $delete_wire$169975
+  wire $delete_wire$169976
+  wire $delete_wire$169977
+  wire $delete_wire$169978
+  wire $delete_wire$169979
+  wire $delete_wire$169980
+  wire $delete_wire$169981
+  wire $delete_wire$169982
+  wire $delete_wire$169983
+  wire $delete_wire$169984
+  wire $delete_wire$169985
+  wire $delete_wire$169986
+  wire $delete_wire$169987
+  wire $delete_wire$169988
+  wire $delete_wire$169989
+  wire $delete_wire$169990
+  wire $delete_wire$169991
+  wire $delete_wire$169992
+  wire $delete_wire$169993
+  wire $delete_wire$169994
+  wire $delete_wire$169995
+  wire $delete_wire$169996
+  wire $delete_wire$169997
+  wire $delete_wire$169998
+  wire $delete_wire$169999
+  wire $delete_wire$170000
+  wire $delete_wire$170001
+  wire $delete_wire$170002
+  wire $delete_wire$170003
+  wire $delete_wire$170004
+  wire $delete_wire$170005
+  wire $delete_wire$170006
+  wire $delete_wire$170007
+  wire $delete_wire$170008
+  wire $delete_wire$170009
+  wire $delete_wire$170010
+  wire $delete_wire$170011
+  wire $delete_wire$170012
+  wire $delete_wire$170013
+  wire $delete_wire$170014
+  wire $delete_wire$170015
+  wire $delete_wire$170016
+  wire $delete_wire$170017
+  wire $delete_wire$170018
+  wire $delete_wire$170019
+  wire $delete_wire$170020
+  wire $delete_wire$170021
+  wire $delete_wire$170022
+  wire $delete_wire$170023
+  wire $delete_wire$170024
+  wire $delete_wire$170025
+  wire $delete_wire$170026
+  wire $delete_wire$170027
+  wire $delete_wire$170028
+  wire $delete_wire$170029
+  wire $delete_wire$170030
+  wire $delete_wire$170031
+  wire $delete_wire$170032
+  wire $delete_wire$170033
+  wire $delete_wire$170034
+  wire $delete_wire$170035
+  wire $delete_wire$170036
+  wire $delete_wire$170037
+  wire $delete_wire$170038
+  wire $delete_wire$170039
+  wire $delete_wire$170040
+  wire $delete_wire$170041
+  wire $delete_wire$170042
+  wire $delete_wire$170043
+  wire $delete_wire$170044
+  wire $delete_wire$170045
+  wire $delete_wire$170046
+  wire $delete_wire$170047
+  wire $delete_wire$170048
+  wire $delete_wire$170049
+  wire $delete_wire$170050
+  wire $delete_wire$170051
+  wire $delete_wire$170052
+  wire $delete_wire$170053
+  wire $delete_wire$170054
+  wire $delete_wire$170055
+  wire $delete_wire$170056
+  wire $delete_wire$170057
+  wire $delete_wire$170058
+  wire $delete_wire$170059
+  wire $delete_wire$170635
+  wire $delete_wire$170636
+  wire $delete_wire$170637
+  wire $delete_wire$170638
+  wire $delete_wire$170639
+  wire $delete_wire$170640
+  wire $delete_wire$170641
+  wire $delete_wire$170642
+  wire $delete_wire$170643
+  wire $delete_wire$170644
+  wire $delete_wire$170645
+  wire $delete_wire$170646
+  wire $delete_wire$170647
+  wire $delete_wire$170648
+  wire $delete_wire$170649
+  wire $delete_wire$170650
+  wire $delete_wire$170651
+  wire $delete_wire$170652
+  wire $delete_wire$170653
+  wire $delete_wire$170654
+  wire $delete_wire$170655
+  wire $delete_wire$170656
+  wire $delete_wire$170657
+  wire $delete_wire$170658
+  wire $delete_wire$170659
+  wire $delete_wire$170660
+  wire $delete_wire$170661
+  wire $delete_wire$170662
+  wire $delete_wire$170663
+  wire $delete_wire$170664
+  wire $delete_wire$170665
+  wire $delete_wire$170666
+  wire $delete_wire$170667
+  wire $delete_wire$170668
+  wire $delete_wire$170669
+  wire $delete_wire$170670
+  wire $delete_wire$170749
+  wire $delete_wire$170750
+  wire $delete_wire$170751
+  wire $delete_wire$170752
+  wire $delete_wire$170753
+  wire $delete_wire$170754
+  wire $delete_wire$170755
+  wire width 2 $delete_wire$170756
+  wire width 2 $delete_wire$170757
+  wire $delete_wire$170758
+  wire $delete_wire$170759
+  wire $delete_wire$170760
+  wire $delete_wire$170761
+  wire $delete_wire$170762
+  wire $delete_wire$170763
+  wire $delete_wire$170764
+  wire $delete_wire$170765
+  wire $delete_wire$170766
+  wire $delete_wire$170767
+  wire $delete_wire$170768
+  wire $delete_wire$170769
+  wire $delete_wire$170770
+  wire $delete_wire$170771
+  wire $delete_wire$170772
+  wire $delete_wire$170773
+  wire $delete_wire$170774
+  wire $delete_wire$170775
+  wire $delete_wire$170859
+  wire $delete_wire$170860
+  wire $delete_wire$170861
+  wire $delete_wire$170862
+  wire $delete_wire$170863
+  wire $delete_wire$170864
+  wire $delete_wire$170865
+  wire $delete_wire$170866
+  wire $delete_wire$170867
+  wire $delete_wire$170868
+  wire $delete_wire$170869
+  wire $delete_wire$170870
+  wire $delete_wire$170871
+  wire $delete_wire$170872
+  wire $delete_wire$170873
+  wire $delete_wire$170874
+  wire $delete_wire$170875
+  wire $delete_wire$170876
+  wire $delete_wire$170877
+  wire $delete_wire$170878
+  wire $delete_wire$170879
+  wire $delete_wire$170880
+  wire $delete_wire$170881
+  wire $delete_wire$170882
+  wire $delete_wire$170996
+  wire $delete_wire$170997
+  wire $delete_wire$170998
+  wire $delete_wire$170999
+  wire $delete_wire$171000
+  wire $delete_wire$171001
+  wire $delete_wire$171002
+  wire $delete_wire$171003
+  wire $delete_wire$171004
+  wire $delete_wire$171005
+  wire $delete_wire$171006
+  wire $delete_wire$171007
+  wire $delete_wire$171008
+  wire $delete_wire$171009
+  wire $delete_wire$171010
+  wire $delete_wire$171011
+  wire $delete_wire$171035
+  wire $delete_wire$171036
+  wire $delete_wire$171037
+  wire $delete_wire$171038
+  wire $delete_wire$171039
+  wire $delete_wire$171040
+  wire $delete_wire$171041
+  wire $delete_wire$171042
+  wire $delete_wire$171043
+  wire $delete_wire$171044
+  wire $delete_wire$171045
+  wire $delete_wire$171046
+  wire $delete_wire$171047
+  wire $delete_wire$171048
+  wire $delete_wire$171049
+  wire $delete_wire$171172
+  wire $delete_wire$171173
+  wire $delete_wire$171174
+  wire $delete_wire$171175
+  wire $delete_wire$171176
+  wire $delete_wire$171177
+  wire $delete_wire$171178
+  wire $delete_wire$171179
+  wire $delete_wire$171180
+  wire $delete_wire$171181
+  wire $delete_wire$171182
+  wire $delete_wire$171183
+  wire $delete_wire$171184
+  wire $delete_wire$171185
+  wire $delete_wire$171186
+  wire $delete_wire$171187
+  wire $delete_wire$171188
+  wire $delete_wire$171189
+  wire $delete_wire$171190
+  wire width 2 $delete_wire$171200
+  wire width 2 $delete_wire$171201
+  wire $delete_wire$171202
+  wire $delete_wire$171203
+  wire $delete_wire$171204
+  wire $delete_wire$171205
+  wire $delete_wire$171206
+  wire $delete_wire$171207
+  wire $delete_wire$171226
+  wire $delete_wire$171227
+  wire $delete_wire$171228
+  wire $delete_wire$171229
+  wire $delete_wire$171230
+  wire $delete_wire$171231
+  wire $delete_wire$171232
+  wire $delete_wire$171254
+  wire $delete_wire$171255
+  wire $delete_wire$171256
+  wire $delete_wire$171257
+  wire $delete_wire$171258
+  wire $delete_wire$171259
+  wire $delete_wire$171267
+  wire $delete_wire$171268
+  wire $delete_wire$171269
+  wire $delete_wire$171270
+  wire $delete_wire$171271
+  wire $delete_wire$171272
+  wire $delete_wire$171314
+  wire $delete_wire$171315
+  wire $delete_wire$171316
+  wire $delete_wire$171317
+  wire $delete_wire$171318
+  wire $delete_wire$171338
+  wire $delete_wire$171339
+  wire $delete_wire$171340
+  wire $delete_wire$171341
+  wire $delete_wire$171350
+  wire $delete_wire$171351
+  wire $delete_wire$171352
+  wire $delete_wire$171353
+  wire $delete_wire$171354
+  wire $delete_wire$171355
+  wire $delete_wire$171356
+  wire $delete_wire$171357
+  wire $delete_wire$171358
+  wire $delete_wire$171359
+  wire $delete_wire$171360
+  wire width 2 $delete_wire$171361
+  wire $delete_wire$171362
+  wire $delete_wire$171371
+  wire $delete_wire$171372
+  wire $delete_wire$171373
+  wire $delete_wire$171374
+  wire $delete_wire$171387
+  wire $delete_wire$171388
+  wire $delete_wire$171389
+  wire $delete_wire$171390
+  wire $delete_wire$171408
+  wire $delete_wire$171409
+  wire $delete_wire$171441
+  wire $delete_wire$171442
+  wire $delete_wire$171449
+  wire $delete_wire$171450
+  wire $delete_wire$171454
+  wire $delete_wire$171455
+  wire $delete_wire$171471
+  wire $delete_wire$171472
+  wire $delete_wire$171477
+  wire $delete_wire$171501
+  wire $delete_wire$171502
+  wire $delete_wire$171507
+  wire $delete_wire$171512
+  wire $delete_wire$171513
+  wire $delete_wire$171514
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323_Y
+  wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322_Y
+  wire \N2231
+  wire \N3558
+  attribute \unused_bits "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31"
+  wire width 32 \dcsr_d
+  wire \dcsr_q_prv__0_
+  cell $adff $procdff$137332
+    parameter \ARST_POLARITY 0
+    parameter \ARST_VALUE 1'1
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \ARST $delete_wire$170004
+    connect \CLK $delete_wire$171206
+    connect \D \dcsr_d [0]
+    connect \Q \dcsr_q_prv__0_
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216087$6334
+    parameter \WIDTH 32
+    connect \A { $delete_wire$170875 $delete_wire$171472 $delete_wire$171181 $delete_wire$169735 $delete_wire$169994 $delete_wire$169963 $delete_wire$170670 $delete_wire$169702 $delete_wire$169975 $delete_wire$170002 $delete_wire$169641 $delete_wire$171011 $delete_wire$171006 $delete_wire$171173 $delete_wire$171387 $delete_wire$170769 $delete_wire$170881 $delete_wire$169743 $delete_wire$169731 $delete_wire$169710 $delete_wire$169756 $delete_wire$170018 $delete_wire$169779 $delete_wire$170037 $delete_wire$169794 $delete_wire$171339 $delete_wire$171256 $delete_wire$171205 $delete_wire$169670 $delete_wire$171352 $delete_wire$171315 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333_Y
+    connect \S $delete_wire$169809
+    connect \Y { $delete_wire$169830 $delete_wire$171390 $delete_wire$169837 $delete_wire$169679 $delete_wire$169677 $delete_wire$169767 $delete_wire$169828 $delete_wire$170038 $delete_wire$169704 $delete_wire$169653 $delete_wire$169707 $delete_wire$169684 $delete_wire$169986 $delete_wire$169712 $delete_wire$170033 $delete_wire$169759 $delete_wire$171513 $delete_wire$170012 $delete_wire$170876 $delete_wire$170007 $delete_wire$169965 $delete_wire$169825 $delete_wire$169655 $delete_wire$169839 $delete_wire$170034 $delete_wire$170042 $delete_wire$171338 $delete_wire$169833 $delete_wire$169762 $delete_wire$169835 $delete_wire$169764 \N2231 }
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333
+    parameter \WIDTH 32
+    connect \A { $delete_wire$170014 $delete_wire$171257 $delete_wire$170770 $delete_wire$169725 $delete_wire$170873 $delete_wire$171514 $delete_wire$170870 $delete_wire$169692 $delete_wire$171184 $delete_wire$170045 $delete_wire$169649 $delete_wire$170859 $delete_wire$171455 $delete_wire$170053 $delete_wire$170044 $delete_wire$170768 $delete_wire$170659 $delete_wire$169742 $delete_wire$169730 $delete_wire$169718 $delete_wire$169741 $delete_wire$170019 $delete_wire$169778 $delete_wire$170024 $delete_wire$169807 $delete_wire$171046 $delete_wire$171374 $delete_wire$170861 $delete_wire$169669 $delete_wire$171182 $delete_wire$171388 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332_Y
+    connect \S $delete_wire$169810
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169820 $delete_wire$171507 $delete_wire$171441 $delete_wire$169724 $delete_wire$169992 $delete_wire$169691 $delete_wire$171356 $delete_wire$169700 $delete_wire$169977 $delete_wire$170046 $delete_wire$169648 $delete_wire$170774 $delete_wire$171038 $delete_wire$171005 $delete_wire$170057 $delete_wire$171226 $delete_wire$170874 $delete_wire$169755 $delete_wire$169729 $delete_wire$171450 $delete_wire$169754 $delete_wire$170020 $delete_wire$169777 $delete_wire$170025 $delete_wire$169806 $delete_wire$170643 $delete_wire$171177 $delete_wire$171449 $delete_wire$169668 $delete_wire$171512 $delete_wire$171501 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331_Y
+    connect \S $delete_wire$169997
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169819 $delete_wire$170772 $delete_wire$170773 $delete_wire$169723 $delete_wire$169990 $delete_wire$169690 $delete_wire$170669 $delete_wire$169699 $delete_wire$169978 $delete_wire$170047 $delete_wire$169647 $delete_wire$171049 $delete_wire$171007 $delete_wire$170872 $delete_wire$170056 $delete_wire$171004 $delete_wire$171202 $delete_wire$169793 $delete_wire$169728 $delete_wire$170664 $delete_wire$169753 $delete_wire$170021 $delete_wire$169776 $delete_wire$170026 $delete_wire$169805 $delete_wire$170644 $delete_wire$171008 $delete_wire$170657 $delete_wire$169658 $delete_wire$171003 $delete_wire$170749 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330_Y
+    connect \S $delete_wire$169826
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330
+    parameter \WIDTH 32
+    connect \A { 4'0100 $delete_wire$169823 2'00 $delete_wire$169822 1'0 $delete_wire$169781 $delete_wire$170757 }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329_Y
+    connect \S $delete_wire$170006
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169818 $delete_wire$170762 $delete_wire$170868 $delete_wire$169722 $delete_wire$169991 $delete_wire$169689 $delete_wire$170642 $delete_wire$169698 $delete_wire$169979 $delete_wire$170048 $delete_wire$169646 $delete_wire$171409 $delete_wire$171259 $delete_wire$170043 $delete_wire$170055 $delete_wire$171471 $delete_wire$170646 $delete_wire$169792 $delete_wire$169727 $delete_wire$169740 $delete_wire$169752 $delete_wire$170022 $delete_wire$169775 $delete_wire$170027 $delete_wire$169804 $delete_wire$170666 $delete_wire$170663 $delete_wire$171179 $delete_wire$169666 $delete_wire$171186 $delete_wire$170655 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328_Y
+    connect \S $delete_wire$169972
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169817 $delete_wire$171190 $delete_wire$171408 $delete_wire$169721 $delete_wire$171002 $delete_wire$169688 $delete_wire$171270 $delete_wire$169697 $delete_wire$169980 $delete_wire$169982 $delete_wire$169645 $delete_wire$171180 $delete_wire$169771 $delete_wire$170860 $delete_wire$170054 $delete_wire$171009 $delete_wire$170639 $delete_wire$169791 $delete_wire$170879 $delete_wire$169739 $delete_wire$169751 $delete_wire$170049 $delete_wire$169774 $delete_wire$170028 $delete_wire$169803 $delete_wire$170645 $delete_wire$169989 $delete_wire$171272 $delete_wire$169665 $delete_wire$171174 $delete_wire$170653 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327_Y
+    connect \S $delete_wire$170036
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169816 $delete_wire$171228 $delete_wire$171454 $delete_wire$169720 $delete_wire$170997 $delete_wire$169687 $delete_wire$170649 $delete_wire$169696 $delete_wire$169981 $delete_wire$170050 $delete_wire$169644 $delete_wire$170760 $delete_wire$169786 $delete_wire$170862 $delete_wire$170032 $delete_wire$171389 $delete_wire$171043 $delete_wire$169790 $delete_wire$169749 $delete_wire$169738 $delete_wire$169750 $delete_wire$169983 $delete_wire$169773 $delete_wire$170029 $delete_wire$169802 $delete_wire$170660 $delete_wire$169962 $delete_wire$170658 $delete_wire$169664 $delete_wire$170751 $delete_wire$170640 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326_Y
+    connect \S $delete_wire$169705
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169815 $delete_wire$171372 $delete_wire$171175 $delete_wire$169719 $delete_wire$171044 $delete_wire$169686 $delete_wire$171231 $delete_wire$169695 $delete_wire$170008 $delete_wire$170052 $delete_wire$169643 $delete_wire$170996 $delete_wire$169785 $delete_wire$170865 $delete_wire$170636 $delete_wire$171185 $delete_wire$171188 $delete_wire$169789 $delete_wire$171045 $delete_wire$169737 $delete_wire$169765 $delete_wire$171268 $delete_wire$169772 $delete_wire$170016 $delete_wire$169801 $delete_wire$170665 $delete_wire$170058 $delete_wire$169961 $delete_wire$169663 $delete_wire$171502 $delete_wire$170652 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325_Y
+    connect \S $delete_wire$170650
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169814 $delete_wire$170753 $delete_wire$171176 $delete_wire$169709 $delete_wire$170999 $delete_wire$169685 $delete_wire$170647 $delete_wire$169694 $delete_wire$169999 $delete_wire$170051 $delete_wire$169642 $delete_wire$170863 $delete_wire$169784 $delete_wire$170755 $delete_wire$170754 $delete_wire$171204 $delete_wire$171373 $delete_wire$169788 $delete_wire$170059 $delete_wire$169736 $delete_wire$169748 $delete_wire$171351 $delete_wire$169787 $delete_wire$171340 $delete_wire$169800 $delete_wire$170638 $delete_wire$169970 $delete_wire$169974 $delete_wire$169662 $delete_wire$170764 $delete_wire$170651 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324_Y
+    connect \S $delete_wire$169996
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169813 $delete_wire$171229 $delete_wire$170765 $delete_wire$169717 $delete_wire$171035 $delete_wire$169675 $delete_wire$170637 $delete_wire$169693 $delete_wire$170000 $delete_wire$171000 $delete_wire$169650 $delete_wire$171442 $delete_wire$169783 $delete_wire$170882 $delete_wire$171318 $delete_wire$171010 $delete_wire$171357 $delete_wire$169821 $delete_wire$170880 $delete_wire$169726 $delete_wire$169747 $delete_wire$169984 $delete_wire$169770 $delete_wire$170031 $delete_wire$169799 $delete_wire$171048 $delete_wire$169969 $delete_wire$170656 $delete_wire$169661 $delete_wire$171354 $delete_wire$170661 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323_Y
+    connect \S $delete_wire$169671
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169998 $delete_wire$171350 $delete_wire$170759 $delete_wire$169716 $delete_wire$169993 $delete_wire$169683 $delete_wire$170654 $delete_wire$169667 $delete_wire$170001 $delete_wire$171371 $delete_wire$169674 $delete_wire$170667 $delete_wire$169782 $delete_wire$171187 $delete_wire$170878 $delete_wire$170766 $delete_wire$171254 $delete_wire$169796 $delete_wire$170877 $delete_wire$169734 $delete_wire$169746 $delete_wire$171207 $delete_wire$169769 $delete_wire$170009 $delete_wire$169798 $delete_wire$171172 $delete_wire$169968 $delete_wire$171271 $delete_wire$169660 $delete_wire$171232 $delete_wire$170662 \dcsr_q_prv__0_ }
+    connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322_Y
+    connect \S $delete_wire$169831
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322
+    parameter \WIDTH 32
+    connect \A { $delete_wire$169811 $delete_wire$171355 $delete_wire$170763 $delete_wire$169715 $delete_wire$171039 $delete_wire$169682 $delete_wire$169988 $delete_wire$169657 $delete_wire$170015 $delete_wire$171317 $delete_wire$169673 $delete_wire$170866 $delete_wire$169768 $delete_wire$170998 $delete_wire$170752 $delete_wire$170023 $delete_wire$170767 $delete_wire$169795 $delete_wire$170030 $delete_wire$169733 $delete_wire$169745 $delete_wire$171360 $delete_wire$169834 $delete_wire$170010 $delete_wire$169976 $delete_wire$171203 $delete_wire$169967 $delete_wire$171477 $delete_wire$169659 $delete_wire$171230 $delete_wire$170641 \dcsr_q_prv__0_ }
+    connect \B $delete_wire$169713
+    connect \S $delete_wire$171001
+    connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322_Y
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:217099$7332
+    parameter \WIDTH 32
+    connect \A { $delete_wire$170013 $delete_wire$171353 $delete_wire$171037 $delete_wire$169714 $delete_wire$171269 $delete_wire$169681 $delete_wire$170668 $delete_wire$169656 $delete_wire$170003 $delete_wire$171189 $delete_wire$169672 $delete_wire$169960 $delete_wire$169780 $delete_wire$170775 $delete_wire$170871 $delete_wire$170864 $delete_wire$171183 $delete_wire$169808 $delete_wire$170017 $delete_wire$169732 $delete_wire$169744 $delete_wire$171359 $delete_wire$171041 $delete_wire$171040 $delete_wire$170761 $delete_wire$170635 $delete_wire$169966 $delete_wire$169971 $delete_wire$169701 $delete_wire$170648 $delete_wire$171255 \dcsr_q_prv__0_ }
+    connect \B { $delete_wire$169829 $delete_wire$171316 $delete_wire$169836 $delete_wire$169678 $delete_wire$169676 $delete_wire$169766 $delete_wire$169827 $delete_wire$170039 $delete_wire$169703 $delete_wire$169652 $delete_wire$169706 $delete_wire$169708 $delete_wire$169987 $delete_wire$169711 $delete_wire$169985 $delete_wire$169758 $delete_wire$169973 $delete_wire$170011 $delete_wire$170869 $delete_wire$169812 $delete_wire$169964 $delete_wire$169824 $delete_wire$169654 $delete_wire$169838 $delete_wire$170035 $delete_wire$169840 $delete_wire$171341 $delete_wire$169832 $delete_wire$169761 $delete_wire$169797 $delete_wire$169763 \N2231 }
+    connect \S $delete_wire$169760
+    connect \Y { \dcsr_d [31:9] $delete_wire$171047 $delete_wire$170040 $delete_wire$170750 \dcsr_d [5:2] $delete_wire$171227 \N3558 }
+  end
+  cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:217233$7498
+    parameter \WIDTH 5
+    connect \A { $delete_wire$169995 $delete_wire$169651 $delete_wire$171042 $delete_wire$171201 }
+    connect \B { $delete_wire$170867 $delete_wire$170041 $delete_wire$171178 $delete_wire$171358 \N3558 }
+    connect \S $delete_wire$170771
+    connect \Y { \dcsr_d [8:6] \dcsr_d [1:0] }
+  end
+end

tests/opt/opt_dff-simplify.ys

@@ -0,0 +1,58 @@
+# 5279 issue
+# Check only for complimentary patterns elimination
+
+read_rtlil opt_dff-simplify.il
+
+select -assert-count 0 t:$adffe
+select -assert-count 1 t:$adff
+select -assert-count 0 t:$ne
+
+opt_dff
+
+select -assert-count 1 t:$adffe
+select -assert-count 0 t:$adff
+
+select -assert-count 8 t:$ne r:A_WIDTH=3 %i
+select -assert-count 5 t:$ne r:A_WIDTH=2 %i
+
+select -assert-none t:$ne r:A_WIDTH=13 %i
+select -assert-none t:$ne r:A_WIDTH=14 %i
+select -assert-none t:$ne r:A_WIDTH=15 %i
+select -assert-none t:$ne r:A_WIDTH=10 %i
+select -assert-none t:$ne r:A_WIDTH=12 %i
+select -assert-none t:$ne r:A_WIDTH=11 %i
+
+# Check for both complimentary and redundancy elimination
+
+read_verilog << EOT
+module test(input clk, input h, input i, input m, output reg p);
+  wire D;
+  wire a;
+  wire j;
+  wire c;
+  wire mux_test;
+  wire n;
+
+  always @(posedge clk)
+    p <= D;
+  assign j = n ? 1'hx : a;
+  assign a = i ? mux_test : p;
+  assign D = m ? h : j;
+  assign c = n ? 1'hx : p;
+  assign mux_test = m ? 1'hx : c;
+endmodule
+EOT
+
+cd test
+proc
+
+select -assert-count 0 t:$dffe
+select -assert-count 1 t:$dff
+select -assert-count 0 t:$ne
+
+opt_dff
+
+select -assert-count 1 t:$dffe
+select -assert-count 0 t:$dff
+select -assert-count 1 t:$ne r:A_WIDTH=2 %i
+select -assert-none t:$ne r:A_WIDTH=3 %i

tests/opt/opt_expr_shift.ys

@@ -20,7 +20,11 @@ module top (
 	output wire        [7:0] sshr_uu,
 	output wire signed [7:0] sshr_us,
 	output wire        [7:0] sshr_su,
-	output wire signed [7:0] sshr_ss
+	output wire signed [7:0] sshr_ss,
+	output wire        [7:0] shiftx_uu,
+	output wire signed [7:0] shiftx_us,
+	output wire        [7:0] shiftx_su,
+	output wire signed [7:0] shiftx_ss
 );
 	assign  shl_uu = in_u << 20;
 	assign  shl_us = in_u << 20;
@@ -38,9 +42,20 @@ module top (
 	assign sshr_us = in_u >>> 20;
 	assign sshr_su = in_s >>> 20;
 	assign sshr_ss = in_s >>> 20;
+	wire [7:0] shamt = 20;
+	assign shiftx_uu = in_u[shamt +: 8];
+	assign shiftx_us = in_u[shamt +: 8];
+	assign shiftx_su = in_s[shamt +: 8];
+	assign shiftx_ss = in_s[shamt +: 8];
 endmodule
 EOT
 
+select -assert-count 4 t:$shl
+select -assert-count 4 t:$shr
+select -assert-count 4 t:$sshl
+select -assert-count 4 t:$sshr
+select -assert-count 4 t:$shiftx
+
 equiv_opt opt_expr
 
 design -load postopt
@@ -48,3 +63,98 @@ select -assert-none t:$shl
 select -assert-none t:$shr
 select -assert-none t:$sshl
 select -assert-none t:$sshr
+select -assert-none t:$shiftx
+
+design -reset
+
+read_verilog <<EOT
+module top (
+	input  wire        [3:0]  in,
+	output wire        [7:0]  shl,
+	output wire        [7:0]  shr,
+	output wire        [7:0] sshl,
+	output wire        [7:0] sshr,
+	output wire        [7:0] shiftx,
+
+	output wire        [7:0]  shl_s,
+	output wire        [7:0]  shr_s,
+	output wire        [7:0] sshl_s,
+	output wire        [7:0] sshr_s,
+	output wire        [7:0] shiftx_s,
+);
+	assign  shl = in << 36'hfffffffff;
+	assign  shr = in >> 36'hfffffffff;
+	assign sshl = in <<< 36'hfffffffff;
+	assign sshr = in >>> 36'hfffffffff;
+	assign shiftx = in[36'hfffffffff +: 8];
+
+	wire signed [35:0] shamt = 36'hfffffffff;
+	assign  shl_s = in << shamt;
+	assign  shr_s = in >> shamt;
+	assign sshl_s = in <<< shamt;
+	assign sshr_s = in >>> shamt;
+	assign shiftx_s = in[shamt +: 8];
+endmodule
+EOT
+
+select -assert-count 2 t:$shl
+select -assert-count 2 t:$shr
+select -assert-count 2 t:$sshl
+select -assert-count 2 t:$sshr
+select -assert-count 1 t:$shiftx
+
+equiv_opt opt_expr
+
+design -load postopt
+select -assert-none t:$shl
+select -assert-none t:$shr
+select -assert-none t:$sshl
+select -assert-none t:$sshr
+select -assert-none t:$shiftx
+
+design -reset
+
+read_verilog <<EOT
+module top (
+	input  wire        [3:0]  in,
+	output wire        [7:0]  shl,
+	output wire        [7:0]  shr,
+	output wire        [7:0] sshl,
+	output wire        [7:0] sshr,
+	output wire        [7:0] shiftx,
+
+	output wire        [7:0]  shl_s,
+	output wire        [7:0]  shr_s,
+	output wire        [7:0] sshl_s,
+	output wire        [7:0] sshr_s,
+	output wire        [7:0] shiftx_s,
+);
+	assign  shl = in << 32'hffffffff;
+	assign  shr = in >> 32'hffffffff;
+	assign sshl = in <<< 32'hffffffff;
+	assign sshr = in >>> 32'hffffffff;
+	assign shiftx = in[32'hffffffff +: 8];
+
+	wire signed [31:0] shamt = 32'hffffffff;
+	assign  shl_s = in << shamt;
+	assign  shr_s = in >> shamt;
+	assign sshl_s = in <<< shamt;
+	assign sshr_s = in >>> shamt;
+	assign shiftx_s = in[shamt +: 8];
+endmodule
+EOT
+
+select -assert-count 2 t:$shl
+select -assert-count 2 t:$shr
+select -assert-count 2 t:$sshl
+select -assert-count 2 t:$sshr
+select -assert-count 1 t:$shiftx
+
+equiv_opt opt_expr
+
+design -load postopt
+select -assert-none t:$shl
+select -assert-none t:$shr
+select -assert-none t:$sshl
+select -assert-none t:$sshr
+select -assert-none t:$shiftx

tests/opt/opt_hier.tcl

@@ -0,0 +1,34 @@
+yosys -import
+
+# per each opt_hier_*.v source file, confirm flattening and hieropt+flattening
+# are combinationally equivalent
+foreach fn [glob opt_hier_*.v] {
+	log -header "Test $fn"
+	log -push
+	design -reset
+
+	read_verilog $fn
+	hierarchy -auto-top
+	prep -top top
+	design -save start
+	flatten
+	design -save gold
+	design -load start
+	opt -hier
+	# check any instances marked `should_get_optimized_out` were
+	# indeed optimized out
+	select -assert-none a:should_get_optimized_out
+	dump
+	flatten
+	design -save gate
+
+	design -reset
+	design -copy-from gold -as gold A:top
+	design -copy-from gate -as gate A:top
+	yosys rename -hide
+	equiv_make gold gate equiv
+	equiv_induct equiv
+	equiv_status -assert equiv
+
+	log -pop
+}

tests/opt/opt_hier_simple1.v

@@ -0,0 +1,8 @@
+module m(input a, output y1, output y2);
+	assign y1 = a;
+	assign y2 = a;
+endmodule
+
+module top(input a, output y2, output y1);
+	m inst(.a(a), .y1(y1), .y2(y2));
+endmodule

tests/opt/opt_hier_simple2.v

@@ -0,0 +1,7 @@
+module m(input [3:0] i, output [3:0] y);
+	assign y = i + 1;
+endmodule
+
+module top(output [3:0] y);
+	m inst(.i(4), .y(y));
+endmodule

tests/opt/opt_hier_test1.v

@@ -0,0 +1,22 @@
+(* blackbox *)
+module bb(output y);
+endmodule
+
+// all instances of `m` tie together a[1], a[2]
+// this can be used to conclude y[0]=0
+module m(input [3:0] a, output [1:0] y, output x);
+	assign y[0] = a[1] != a[2];
+	assign x = a[0] ^ a[3];
+	(* should_get_optimized_out *)
+	bb bb1(.y(y[1]));
+endmodule
+
+module top(input j, output z, output [2:0] x);
+	wire [1:0] y1;
+	wire [1:0] y2;
+	wire [1:0] y3;
+	m inst1(.a(0), .y(y1), .x(x[0]));
+	m inst2(.a(15), .y(y2), .x(x[1]));
+	m inst3(.a({1'b1, j, j, 1'b0}), .y(y3), .x(x[2]));
+	assign z = (&y1) ^ (&y2) ^ (&y3);
+endmodule

tests/opt/run-test.sh

@@ -1,4 +1,4 @@
 #!/usr/bin/env bash
 set -eu
 source ../gen-tests-makefile.sh
-generate_mk --yosys-scripts
+generate_mk --yosys-scripts --tcl-scripts

tests/peepopt/.gitignore

@@ -1 +0,0 @@
-/*.log

tests/proc/.gitignore

@@ -1 +0,0 @@
-*.log

tests/proc/case_attr.ys

@@ -0,0 +1,57 @@
+read_verilog -sv << EOF
+module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
+	always @* begin
+		W = F;
+		(* full_case *)
+		case (C)
+			A: W = D;
+			B: W = E;
+		endcase
+	end
+
+	always @* begin
+		X = F;
+		case (C)
+			A: X = D;
+			B: X = E;
+		endcase
+	end
+
+	always @* begin
+		Y = F;
+		(* full_case, parallel_case *)
+		case (C)
+			A: Y = D;
+			B: Y = E;
+		endcase
+	end
+
+	always @* begin
+		Z = F;
+		(* parallel_case *)
+		case (C)
+			A: Z = D;
+			B: Z = E;
+		endcase
+	end
+endmodule
+EOF
+prep
+# For the ones which use full_case, the F signal shouldn't be included in
+# the input cone of W and Y.
+select -set full o:W o:Y %u %ci*
+select -assert-none i:F @full %i
+select -assert-count 1 o:X %ci* i:F %i
+select -assert-count 1 o:Z %ci* i:F %i
+
+# And for parallel_case there should be 1 $pmux compared to the 2 $mux
+# cells without.
+select -assert-none o:W %ci* t:$pmux %i
+select -assert-none o:X %ci* t:$pmux %i
+select -assert-count 1 o:Y %ci* t:$pmux %i
+select -assert-count 1 o:Z %ci* t:$pmux %i
+
+select -assert-count 2 o:W %ci* t:$mux %i
+select -assert-count 2 o:X %ci* t:$mux %i
+select -assert-none o:Y %ci* t:$mux %i
+select -assert-none o:Z %ci* t:$mux %i

tests/pyosys/run_tests.py

@@ -0,0 +1,46 @@
+import sys
+import shutil
+import shlex
+import subprocess
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+if len(sys.argv) > 2 or len(sys.argv) == 2 and sys.argv[1] != 'yosys':
+	print(f"Usage: {sys.argv[0]} [yosys]")
+	exit(64)
+
+if len(sys.argv) == 2:
+	binary = [str(__file_dir__.parents[1] / "yosys"), "-Qy"]
+else:
+	binary = [sys.executable or shutil.which("python3") or "python3"] # sys.executable can actually be None
+
+tests = __file_dir__.glob("test_*.py")
+
+log_dir = __file_dir__ / "logs"
+try:
+	shutil.rmtree(log_dir)
+except FileNotFoundError:
+	pass
+fail_logs = set()
+for test in tests:
+	print(f"* {test.name} ", end="")
+	log_dir.mkdir(parents=True, exist_ok=True)
+	log = log_dir / (test.stem + ".log")
+	cmd = [*binary, str(test)]
+	log_file = open(log, "w", encoding="utf8")
+	log_file.write(f"$ {shlex.join(cmd)}\n")
+	log_file.flush()
+	result = subprocess.run(cmd, stdout=log_file, stderr=subprocess.STDOUT)
+	if result.returncode == 0:
+		print("OK!")
+	else:
+		print(f"FAILED: {log}")
+		fail_logs.add(log)
+	log_file.close()
+for log in fail_logs:
+	print(f">>> {log}")
+	with open(log, encoding="utf8") as f:
+		print(f.read())
+if len(fail_logs):
+	exit(1)

tests/pyosys/test_data_read.py

@@ -0,0 +1,45 @@
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+d = ys.Design()
+
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass("hierarchy -top spm", d)
+
+name_by_tv_location = []
+name_by_au_location = []
+
+# test both dictionary mapping and equiv operators working fine
+module = None
+print(d.modules_)
+for idstr, module_obj in d.modules_.items():
+	if idstr != ys.IdString("\\spm"):
+		continue
+	if idstr.str() != "\\spm":
+		continue
+	module = module_obj
+	break
+
+assert module == d.top_module(), "top module search failed"
+for name in module.ports:
+	wire = module.wires_[name]
+	name_str = name.str()
+	if name_str.endswith(".d"):  # single reg output, in au
+		name_by_au_location.append(name_str[1:-2])
+	elif name_str.endswith(".q"):  # single reg input, in tv
+		name_by_tv_location.append(name_str[1:-2])
+	else:  # port/boundary scan
+		frm = wire.start_offset + wire.width
+		to = wire.start_offset
+		for i in range(frm - 1, to - 1, -1):
+			bit_name = name_str[1:] + f"\\[{i}\\]"
+			if wire.port_input:
+				name_by_tv_location.append(bit_name)
+			elif wire.port_output:
+				name_by_au_location.append(bit_name)
+
+assert name_by_tv_location == ['x\\[0\\]', 'a\\[31\\]', 'a\\[30\\]', 'a\\[29\\]', 'a\\[28\\]', 'a\\[27\\]', 'a\\[26\\]', 'a\\[25\\]', 'a\\[24\\]', 'a\\[23\\]', 'a\\[22\\]', 'a\\[21\\]', 'a\\[20\\]', 'a\\[19\\]', 'a\\[18\\]', 'a\\[17\\]', 'a\\[16\\]', 'a\\[15\\]', 'a\\[14\\]', 'a\\[13\\]', 'a\\[12\\]', 'a\\[11\\]', 'a\\[10\\]', 'a\\[9\\]', 'a\\[8\\]', 'a\\[7\\]', 'a\\[6\\]', 'a\\[5\\]', 'a\\[4\\]', 'a\\[3\\]', 'a\\[2\\]', 'a\\[1\\]', 'a\\[0\\]', '_315_', '_314_', '_313_', '_312_', '_311_', '_310_', '_309_', '_308_', '_307_', '_306_', '_305_', '_304_', '_303_', '_302_', '_301_', '_300_', '_299_', '_298_', '_297_', '_296_', '_295_', '_294_', '_293_', '_292_', '_291_', '_290_', '_289_', '_288_', '_287_', '_286_', '_285_', '_284_', '_283_', '_282_', '_281_', '_280_', '_279_', '_278_', '_277_', '_276_', '_275_', '_274_', '_273_', '_272_', '_271_', '_270_', '_269_', '_268_', '_267_', '_266_', '_265_', '_264_', '_263_', '_262_', '_261_', '_260_', '_259_', '_258_', '_257_', '_256_', '_255_', '_254_', '_253_', '_252_'], "failed to extract test vector register locations"
+assert name_by_au_location == ['y\\[0\\]', '_315_', '_314_', '_313_', '_312_', '_311_', '_310_', '_309_', '_308_', '_307_', '_306_', '_305_', '_304_', '_303_', '_302_', '_301_', '_300_', '_299_', '_298_', '_297_', '_296_', '_295_', '_294_', '_293_', '_292_', '_291_', '_290_', '_289_', '_288_', '_287_', '_286_', '_285_', '_284_', '_283_', '_282_', '_281_', '_280_', '_279_', '_278_', '_277_', '_276_', '_275_', '_274_', '_273_', '_272_', '_271_', '_270_', '_269_', '_268_', '_267_', '_266_', '_265_', '_264_', '_263_', '_262_', '_261_', '_260_', '_259_', '_258_', '_257_', '_256_', '_255_', '_254_', '_253_', '_252_'], "failed to extract golden output register locations"
+print("ok!")

tests/pyosys/test_dict.py

@@ -0,0 +1,44 @@
+from typing import Mapping
+from pyosys import libyosys as ys
+
+StringToStringDict = ys.StringToStringDict
+
+my_dict = StringToStringDict()
+
+assert isinstance(my_dict, Mapping)
+
+my_dict["foo"] = "bar"
+my_dict.update([("first", "second")])
+my_dict.update({"key": "value"})
+for key, value in my_dict.items():
+    print(key, value)
+
+new_dict = my_dict | {"tomato": "tomato"}
+del new_dict["foo"]
+assert set(my_dict.keys()) == {"first", "key", "foo"}
+assert set(new_dict.keys()) == {"first", "key", "tomato"}
+
+constructor_test_1 = ys.StringToStringDict(new_dict)
+constructor_test_2 = ys.StringToStringDict([("tomato", "tomato")])
+constructor_test_3 = ys.StringToStringDict({ "im running": "out of string ideas" })
+
+the_great_or = constructor_test_1 | constructor_test_2 | constructor_test_3
+
+assert set(the_great_or) ==  {"first", "key", "tomato", "im running"}
+repr_test = eval(repr(the_great_or))
+
+assert repr_test == the_great_or # compare dicts
+assert repr_test == {'tomato': 'tomato', 'first': 'second', 'key': 'value', 'im running': 'out of string ideas', } # compare dict with mapping
+
+before = len(repr_test)
+print(repr_test.popitem())
+assert before - 1 == len(repr_test)
+
+# test noncomparable
+## if ys.CellType ever gets an == operator just disable this section
+uncomparable_value = ys.Globals.yosys_celltypes.cell_types[ys.IdString("$not")]
+
+x = ys.IdstringToCelltypeDict({ ys.IdString("\\a"): uncomparable_value})
+y = ys.IdstringToCelltypeDict({ ys.IdString("\\a"): uncomparable_value})
+
+assert x != y # not comparable

tests/pyosys/test_ecp5_addsub.py

@@ -1,8 +1,8 @@
-import os
+from pathlib import Path
 from pyosys import libyosys as ys
 
-__dir__ = os.path.dirname(os.path.abspath(__file__))
-add_sub = os.path.join(__dir__, "..", "common", "add_sub.v")
+__file_dir__ = Path(__file__).absolute().parent
+add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
 
 base = ys.Design()
 ys.run_pass(f"read_verilog {add_sub}", base)

tests/pyosys/test_idict.py

@@ -0,0 +1,31 @@
+from pyosys import libyosys as ys
+
+my_idict = ys.IdstringIdict()
+print(my_idict(ys.IdString("\\hello"))) # test explicit IdString construction
+print(my_idict("\\world"))
+print(my_idict.get("\\world"))
+try:
+	print(my_idict.get("\\dummy"))
+except IndexError as e:
+	print(f"{repr(e)}")
+print(my_idict[0])
+print(my_idict[1])
+try:
+	print(my_idict[2])
+except IndexError as e:
+	print(f"{repr(e)}")
+
+for i in my_idict:
+	print(i)
+
+current_len = len(my_idict)
+assert current_len == 2, "copy"
+
+my_copy = my_idict.copy()
+my_copy("\\copy")
+assert len(my_idict) == current_len, "copy seemed to have mutate original idict"
+assert len(my_copy) == current_len + 1, "copy not behaving as expected"
+
+current_copy_len = len(my_copy)
+my_copy |= ("\\the", "\\world") # 1 new element
+assert len(my_copy) == current_copy_len + 1, "or operator returned unexpected result"

tests/pyosys/test_idstring_lifetime.py

@@ -0,0 +1,28 @@
+
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+d = ys.Design()
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass("hierarchy -top spm", d)
+
+external_idstring_holder_0 = None
+external_idstring_holder_1 = None
+
+def get_top_module_idstring():
+	global external_idstring_holder_0, external_idstring_holder_1
+	d = ys.Design()
+	ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+	ys.run_pass("hierarchy -top spm", d)
+	external_idstring_holder_0 = d.top_module().name
+	for cell in d.top_module().cells_:
+		print(f"TARGETED: {cell}", flush=True)
+		external_idstring_holder_1 = cell
+		break
+	# d deallocates
+
+get_top_module_idstring()
+print(external_idstring_holder_0, flush=True)
+print(external_idstring_holder_1, flush=True)

tests/pyosys/test_import.py

@@ -0,0 +1,20 @@
+import os
+import sys
+
+from pyosys import libyosys as ys
+
+print(ys)
+
+ys.log("Hello, world!\n")
+
+from pyosys.libyosys import log
+
+print(log)
+
+log("Goodbye, world!\n")
+
+import pyosys
+
+if os.path.basename(sys.executable) == "yosys":
+	# make sure it's not importing the directory
+	assert "built-in" in repr(pyosys)

tests/pyosys/test_indirect_inheritance.py

@@ -0,0 +1,15 @@
+
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+
+d = ys.Design()
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass("hierarchy -top spm", d)
+
+for idstr, cell in d.top_module().cells_.items():
+    cell.set_bool_attribute("\\set")
+    print(cell.attributes)
+    break

tests/pyosys/test_logs.py

@@ -0,0 +1,8 @@
+from pyosys import libyosys as ys
+
+d = ys.Design(); ys.log_header(d, "foo\n")
+ys.log("foo\n")
+ys.log_warning("foo\n")
+ys.log_warning_noprefix("foo\n")
+ys.log_file_info("foo.ys", 1, "foo\n")
+ys.log_file_warning("foo.ys", 1, "foo\n")

tests/pyosys/test_monitor.py

@@ -0,0 +1,22 @@
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+d = ys.Design()
+
+class Monitor(ys.Monitor):
+	def __init__(self):
+		super().__init__()
+		self.mods = []
+
+	def notify_module_add(self, mod):
+		self.mods.append(mod.name.str())
+
+m = Monitor()
+d.monitors = [m]
+
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass("hierarchy -top spm", d)
+
+assert m.mods == ["\\spm"]

tests/pyosys/test_pass.py

@@ -0,0 +1,34 @@
+from pyosys import libyosys as ys
+
+import json
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+class CellStatsPass(ys.Pass):
+	def __init__(self):
+		super().__init__(
+			"cell_stats",
+			"dumps cell statistics in JSON format"
+		)
+
+	def execute(self, args, design):
+		ys.log_header(design, "Dumping cell stats\n")
+		ys.log_push()
+		cell_stats = {}
+		for module in design.all_selected_whole_modules():
+			for cell in module.selected_cells():
+				if cell.type.str() in cell_stats:
+					cell_stats[cell.type.str()] += 1
+				else:
+					cell_stats[cell.type.str()] = 1
+		ys.log(json.dumps(cell_stats))
+		ys.log_pop()
+
+p = CellStatsPass() # registration
+
+design = ys.Design()
+ys.run_pass(f"read_verilog {__file_dir__.parent / 'simple' / 'fiedler-cooley.v'}", design)
+ys.run_pass("prep", design)
+ys.run_pass("opt -full", design)
+ys.run_pass("cell_stats", design)

tests/pyosys/test_set.py

@@ -0,0 +1,42 @@
+# -*- coding: utf-8 -*-
+from pyosys.libyosys import StringSet, StringPool
+
+for cls in [StringSet, StringPool]:
+	print(f"Testing {cls.__name__}...")
+	A = cls()
+	A.add("a")
+
+	B = cls()
+	B = A | {"b"}
+
+	assert A < B
+	assert A <= B
+
+	A.add("b")
+
+	assert A == B
+	assert A <= B
+	assert not A < B
+
+	A.add("c")
+
+	assert A > B
+
+	A &= B
+	assert A == B
+
+	Ø = A - B
+	assert len(Ø) == 0
+
+	C = cls({"A", "B", "C"})
+	D = cls()
+	C |= {"A", "B", "C"}
+	D |= {"C", "D", "E"}
+	c_symdiff_d = (C ^ D)
+	assert c_symdiff_d == {"A", "B", "D", "E"} # compare against iterable
+
+	repr_test = eval(repr(c_symdiff_d))
+	assert c_symdiff_d == repr_test # compare against self
+
+
+print("Done.")

tests/pyosys/test_sigspec_it.py

@@ -0,0 +1,28 @@
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+def _dump_sigbit(bit):
+    if bit.is_wire():
+        if bit.wire.width == 1:
+            return bit.wire.name.str()
+        else:
+            return f"{bit.wire.name} [{bit.offset}]"
+    else:
+        if bit.data == ys.State.S1:
+            return 1
+        elif bit.data == ys.State.S0:
+            return 0
+        else:
+            assert "unknown constants not supported"
+
+d = ys.Design()
+
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass(f"hierarchy -top spm", d)
+module = d.module(r"\spm")
+for conn_from, conn_to in module.connections_:
+    for bit_from, bit_to in zip(conn_from, conn_to):
+        print(f"assign {_dump_sigbit(bit_from)} = {_dump_sigbit(bit_to)};")
+

tests/rpc/.gitignore

@@ -1 +0,0 @@
-*.log

tests/rtlil/.gitignore

@@ -0,0 +1 @@
+/temp

tests/rtlil/bug5424.ys

@@ -0,0 +1,12 @@
+read_rtlil <<EOT
+module \meow
+	wire width 8 \nya
+	wire width 8 output 1 \mrrp
+	wire width 1 input 0 \purr
+	process $cat
+		assign \nya { \mrrp \purr } [7:0]
+	end
+end
+EOT
+
+select -assert-count 1 meow/$cat

tests/rtlil/everything.v

@@ -0,0 +1,57 @@
+module alu(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] operation,
+	output reg [7:0] result,
+	output reg CF,
+	output reg ZF,
+	output reg SF
+);
+
+	localparam ALU_OP_ADD = 4'b0000;
+	localparam ALU_OP_SUB = 4'b0001;
+
+	reg [8:0] tmp;
+
+	always @(posedge clk)
+	begin
+		case (operation)
+			ALU_OP_ADD :
+				tmp = A + B;
+			ALU_OP_SUB :
+				tmp = A - B;
+		endcase
+
+		CF <= tmp[8];
+		ZF <= tmp[7:0] == 0;
+		SF <= tmp[7];
+
+		result <= tmp[7:0];
+	end
+endmodule
+
+module foo(
+    input [7:0] a, input [7:0] b, output [7:0] y
+);
+    wire [7:0] bb;
+    assign b = bb;
+    assign y = a + bb;
+endmodule
+
+module set_param #(
+    parameter [3:0] VALUE = 1'bx
+) (
+    output logic [3:0] out
+);
+    assign out = VALUE;
+endmodule
+
+module use_param (
+    output logic [3:0] a, b, c, d
+);
+    set_param #($signed(1)) spa (a);
+    set_param #('1) spb (b);
+    set_param #(1.1) spc (c);
+    set_param #(1'b1) spd (d);
+endmodule

tests/rtlil/roundtrip-design.sh

@@ -0,0 +1,10 @@
+set -euo pipefail
+YS=../../yosys
+
+mkdir -p temp
+
+$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il"
+diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il
+
+$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il"
+diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il

tests/rtlil/roundtrip-text.sh

@@ -0,0 +1,31 @@
+set -euo pipefail
+YS=../../yosys
+
+mkdir -p temp
+
+# non-POSIX sed -i inconsistency workaround
+remove_empty_lines() {
+    local file="$1"
+    sed '/^$/d' "$file" > temp/tmp
+    mv temp/tmp "$file"
+}
+
+# write_rtlil and dump are equivalent
+$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il"
+remove_empty_lines temp/roundtrip-text.dump.il
+remove_empty_lines temp/roundtrip-text.write.il
+# Trim first line ("Generated by Yosys ...")
+tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il
+diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il
+
+# Loading and writing it out again doesn't change the RTLIL
+$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il"
+remove_empty_lines temp/roundtrip-text.reload.il
+tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il
+diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il
+
+# Hashing differences don't change the RTLIL
+$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il"
+remove_empty_lines temp/roundtrip-text.reload-hash.il
+tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il
+diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il

tests/rtlil/run-test.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+generate_mk --bash --yosys-scripts

tests/sat/.gitignore

@@ -1,4 +1,2 @@
-*.log
-run-test.mk
 *.vcd
 *.fst

tests/sat/fminit_noexpand.ys

@@ -0,0 +1,10 @@
+read_verilog -sv <<EOF
+module thing(input [2:0] in, output reg [2:0] out);
+    assign out = in;
+endmodule
+EOF
+
+select -assert-count 0 t:$eq
+fminit -set out 1'b1
+select -assert-count 1 t:$eq
+select -assert-count 1 t:$eq r:A_WIDTH=1 %i

tests/sat/fminit_seq_width.ys

@@ -0,0 +1,17 @@
+read_verilog -sv -formal <<EOF
+module counter(input clk, input [2:0] rst, input [0:3] rst_val, output logic is_full);
+    logic [1:0] ctr;
+
+    always @(posedge clk)
+        if (rst)
+            ctr <= 0;
+        else
+            ctr <= ctr+1;
+
+    assign is_full = (ctr == 2'b11);
+endmodule
+EOF
+
+hierarchy -check -top counter
+prep -top counter
+fminit -seq rst 0,1,2'b11,2'sb11,rst_val

tests/sdc/alu_sub.sdc

@@ -0,0 +1,70 @@
+###############################################################################
+# Created by write_sdc
+# Fri Oct  3 11:26:00 2025
+###############################################################################
+current_design wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name this_clk -period 1.0000 [get_ports {clk}]
+create_clock -name that_clk -period 2.0000 
+create_clock -name another_clk -period 2.0000 \
+    [list [get_ports {A[0]}]\
+          [get_ports {A[1]}]\
+          [get_ports {A[2]}]\
+          [get_ports {A[3]}]\
+          [get_ports {A[4]}]\
+          [get_ports {A[5]}]\
+          [get_ports {A[6]}]\
+          [get_ports {A[7]}]\
+          [get_ports {B[0]}]\
+          [get_ports {B[1]}]\
+          [get_ports {B[2]}]\
+          [get_ports {B[3]}]\
+          [get_ports {B[4]}]\
+          [get_ports {B[5]}]\
+          [get_ports {B[6]}]\
+          [get_ports {B[7]}]]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[7]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[7]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[7]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[7]}]
+group_path -name operation_group\
+    -through [list [get_nets {alu/operation[0]}]\
+           [get_nets {alu/operation[1]}]\
+           [get_nets {alu/operation[2]}]\
+           [get_nets {alu/operation[3]}]]
+###############################################################################
+# Environment
+###############################################################################
+###############################################################################
+# Design Rules
+###############################################################################

tests/sdc/alu_sub.v

@@ -0,0 +1,62 @@
+module adder(
+    input [7:0] a, input [7:0] b, output [7:0] y
+);
+    assign y = a + b;
+endmodule
+
+module wrapper(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] op,
+	output reg [7:0] result
+);
+	wire CF, ZF, SF;
+	alu alu(
+		.clk(clk),
+		.A(A),
+		.B(B),
+		.operation(op),
+		.result(result),
+		.CF(CF),
+		.ZF(ZF),
+		.SF(SF)
+	);
+endmodule
+
+module alu(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] operation,
+	output reg [7:0] result,
+	output reg CF,
+	output reg ZF,
+	output reg SF
+);
+
+	localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000;
+	localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001;
+
+	reg [8:0] tmp;
+	reg [7:0] added;
+
+	adder adder(.a(A), .b(B), .y(added));
+
+	always @(posedge clk)
+	begin
+		case (operation)
+			ALU_OP_ADD :
+				tmp = added;
+			ALU_OP_SUB :
+				tmp = A - B;
+		endcase
+
+		CF <= tmp[8];
+		ZF <= tmp[7:0] == 0;
+		SF <= tmp[7];
+
+		result <= tmp[7:0];
+	end
+endmodule
+

tests/sdc/alu_sub.ys

@@ -0,0 +1,14 @@
+read_verilog alu_sub.v
+proc
+hierarchy -auto-top
+
+select -assert-mod-count 1 adder
+select -assert-mod-count 1 wrapper
+select -assert-mod-count 1 alu
+
+sdc -keep_hierarchy alu_sub.sdc
+flatten
+
+select -assert-mod-count 0 adder
+select -assert-mod-count 1 wrapper
+select -assert-mod-count 1 alu

tests/sdc/get_foo.sdc

@@ -0,0 +1 @@
+get_foo -bar 1

tests/sdc/run-test.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+generate_mk --yosys-scripts --bash

tests/sdc/side-effects.sdc

@@ -0,0 +1,2 @@
+puts "This should print something:"
+puts [get_ports {A[0]}]

tests/sdc/side-effects.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+
+../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something:
+YOSYS_SDC_MAGIC_NODE_0'

tests/sdc/unknown-getter.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+! ../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter'

tests/select/.gitignore

@@ -1 +0,0 @@
-/*.log

tests/sim/.gitignore

@@ -1,6 +1,3 @@
-*.log
-/run-test.mk
 +*_synth.v
 +*_testbench
-*.out
 *.fst

tests/sim/sim_cycles.ys

@@ -2,7 +2,7 @@ read_verilog dff.v
 prep
 
 # create fst with 20 clock cycles (41 samples, 202ns)
-sim -clock clk -fst sim_cycles.fst -n 20
+sim -clock clk -fst sim_cycles.fst -width 2 -n 20
 
 logger -expect-no-warnings
 
@@ -10,7 +10,7 @@ logger -expect-no-warnings
 logger -expect log "Co-simulating cycle 41" 2
 logger -warn "Co-simulating cycle 42"
 sim -clock clk -r sim_cycles.fst -scope dff -n 21 -sim-cmp
-sim -clock clk -r sim_cycles.fst -scope dff -stop 202 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 41 -sim-cmp
 logger -check-expected
 
 # over limit stops at final step
@@ -18,29 +18,29 @@ logger -expect log "Co-simulating cycle 41" 2
 sim -clock clk -r sim_cycles.fst -scope dff -n 30 -sim-cmp
 # -stop warns for over limit
 logger -nowarn "Stop time is after simulation file end time"
-sim -clock clk -r sim_cycles.fst -scope dff -stop 300 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 50 -sim-cmp
 logger -check-expected
 
 # don't auto step last
 logger -expect log "Co-simulating cycle 40" 2
 logger -warn "Co-simulating cycle 41"
 sim -clock clk -r sim_cycles.fst -scope dff -n 20 -sim-cmp
-sim -clock clk -r sim_cycles.fst -scope dff -stop 200 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 40 -sim-cmp
 logger -check-expected
 
-# -n 10 == -stop 100
+# -n 10 == -stop 20
 # should simulate up to 20 and not more
 logger -expect log "Co-simulating cycle 20" 2
 logger -warn "Co-simulating cycle 21"
 sim -clock clk -r sim_cycles.fst -scope dff -n 10 -sim-cmp
-sim -clock clk -r sim_cycles.fst -scope dff -stop 100 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 20 -sim-cmp
 logger -check-expected
 
-# -n 1 == -stop 10
+# -n 1 == -stop 2
 logger -expect log "Co-simulating cycle 2" 2
 logger -warn "Co-simulating cycle 3"
 sim -clock clk -r sim_cycles.fst -scope dff -n 1 -sim-cmp
-sim -clock clk -r sim_cycles.fst -scope dff -stop 10 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 2 -sim-cmp
 logger -check-expected
 
 # -n 0 == -stop 0

tests/simple/.gitignore

@@ -1,3 +0,0 @@
-*.log
-*.out
-*.err