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https://github.com/YosysHQ/yosys
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parent
e9ff5f7d91
commit
6fe0e00050
4 changed files with 64 additions and 14 deletions
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@ -38,7 +38,11 @@ input PORT_W_WR_EN;
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input [ADDR_BITS-1:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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RAM64x12 _TECHMAP_REPLACE_ (
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`include "brams_defs.vh"
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RAM64x12 #(
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`PARAMS_INIT_uSRAM
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) _TECHMAP_REPLACE_ (
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.R_ADDR(PORT_R_ADDR),
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.R_ADDR_BYPASS(1'b1),
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.R_ADDR_EN(1'b0),
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@ -88,7 +92,11 @@ input PORT_R_RD_EN;
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input [ADDR_BITS-1:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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RAM64x12 _TECHMAP_REPLACE_ (
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`include "brams_defs.vh"
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RAM64x12 #(
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`PARAMS_INIT_uSRAM
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) _TECHMAP_REPLACE_ (
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.R_CLK(PORT_R_CLK),
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.R_ADDR(PORT_R_ADDR),
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.R_ADDR_BYPASS(1'b0),
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