3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 11:26:22 +00:00

pmgen: hold sigmap pointer instead of owning it

This commit is contained in:
Emil J. Tywoniak 2026-04-14 18:05:33 +02:00
parent 394be03d57
commit 6fd7f5c02d
10 changed files with 58 additions and 40 deletions

View file

@ -314,8 +314,10 @@ struct Ice40DspPass : public Pass {
// TODO Disabled signorm because swap_names breaks fanout logic
design->sigNormalize(false);
for (auto module : design->selected_modules())
ice40_dsp_pm(module, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);
for (auto module : design->selected_modules()) {
SigMap sigmap(module);
ice40_dsp_pm(module, &sigmap, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);
}
}
} Ice40DspPass;

View file

@ -48,7 +48,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
cell->setPort(ID(I0), st.lut->getPort(ID(I0)));
auto I3 = st.lut->getPort(ID(I3));
if (pm.sigmap(CI) == pm.sigmap(I3)) {
if ((*pm.sigmap)(CI) == (*pm.sigmap)(I3)) {
cell->setParam(ID(I3_IS_CI), State::S1);
I3 = State::Sx;
}
@ -112,9 +112,10 @@ struct Ice40WrapCarryPass : public Pass {
design->sigNormalize(false);
for (auto module : design->selected_modules()) {
if (!unwrap)
ice40_wrapcarry_pm(module, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
else {
if (!unwrap) {
SigMap sigmap(module);
ice40_wrapcarry_pm(module, &sigmap, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
} else {
for (auto cell : module->selected_cells()) {
if (cell->type != ID($__ICE40_CARRY_WRAPPER))
continue;