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https://github.com/YosysHQ/yosys
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pmgen: hold sigmap pointer instead of owning it
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parent
394be03d57
commit
6fd7f5c02d
10 changed files with 58 additions and 40 deletions
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@ -314,8 +314,10 @@ struct Ice40DspPass : public Pass {
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// TODO Disabled signorm because swap_names breaks fanout logic
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design->sigNormalize(false);
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for (auto module : design->selected_modules())
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ice40_dsp_pm(module, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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ice40_dsp_pm(module, &sigmap, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);
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}
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}
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} Ice40DspPass;
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@ -48,7 +48,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
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cell->setPort(ID(I0), st.lut->getPort(ID(I0)));
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auto I3 = st.lut->getPort(ID(I3));
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if (pm.sigmap(CI) == pm.sigmap(I3)) {
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if ((*pm.sigmap)(CI) == (*pm.sigmap)(I3)) {
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cell->setParam(ID(I3_IS_CI), State::S1);
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I3 = State::Sx;
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}
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@ -112,9 +112,10 @@ struct Ice40WrapCarryPass : public Pass {
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design->sigNormalize(false);
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for (auto module : design->selected_modules()) {
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if (!unwrap)
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ice40_wrapcarry_pm(module, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
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else {
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if (!unwrap) {
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SigMap sigmap(module);
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ice40_wrapcarry_pm(module, &sigmap, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
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} else {
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for (auto cell : module->selected_cells()) {
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if (cell->type != ID($__ICE40_CARRY_WRAPPER))
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continue;
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