From 25aafab86b6c22f711fdd45cdd14f7721cfcffe1 Mon Sep 17 00:00:00 2001
From: Robert O'Callahan <rocallahan@google.com>
Date: Thu, 23 Oct 2025 20:46:11 +0000
Subject: [PATCH] Set `port_id` for Verific PortBus wires

---
 frontends/verific/verific.cc    |  1 +
 tests/verific/port_bus_order.ys | 13 +++++++++++++
 2 files changed, 14 insertions(+)
 create mode 100644 tests/verific/port_bus_order.ys

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index ff8932dac..5790e92f0 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1576,6 +1576,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		SetIter si ;
 		Port *port ;
 		FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
+			wire->port_id = nl->IndexOf(port) + 1;
 			import_attributes(wire->attributes, port->GetNet(), nl, portbus->Size());
 			break;
 		}
diff --git a/tests/verific/port_bus_order.ys b/tests/verific/port_bus_order.ys
new file mode 100644
index 000000000..8732582a2
--- /dev/null
+++ b/tests/verific/port_bus_order.ys
@@ -0,0 +1,13 @@
+verific -sv <<EOT
+module simple (
+  input  [3:0] I2,
+  input  [3:0] I1,
+  output [3:0] result
+);
+  assign result = I2 & I1;
+endmodule
+EOT
+verific -import simple
+
+write_verilog verilog_port_bus_order.out
+!grep -qF 'simple(I2, I1, result)' verilog_port_bus_order.out