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Parse macro call attached semicolon as empty expression

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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
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Lukasz Dalek 2020-06-01 15:25:24 +02:00 • committed by Kamil Rakoczy
parent 7cb56f34b0
commit 6f9be939bd
1 changed files with 1 additions and 1 deletions
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frontends/verilog/verilog_parser.y
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@ -745,7 +745,7 @@ module_body:
module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
enum_decl | struct_decl |
always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
checker_decl:
TOK_CHECKER TOK_ID ';' {