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Respect opt_expr -keepdc as per @cliffordwolf
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2 changed files with 15 additions and 1 deletions
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@ -277,3 +277,17 @@ check
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equiv_opt opt_expr
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design -load postopt
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select -assert-count 1 t:$shift r:A_WIDTH=10 %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y);
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\$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
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endmodule
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EOT
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check
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equiv_opt opt_expr -keepdc
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design -load postopt
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select -assert-count 1 t:$shift r:A_WIDTH=13 %i
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