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Some minor code cleanups in freduce command

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This commit is contained in:
Clifford Wolf 2014-03-07 18:29:04 +01:00
parent 620d51d9f7
commit 6f8865d81a
1 changed files with 5 additions and 5 deletions
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10
passes/sat/freduce.cc
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@ -244,7 +244,6 @@ struct PerformReduction
return 0;
if (sigdepth.count(out) != 0)
return sigdepth.at(out);
sigdepth[out] = 0;
if (drivers.count(out) != 0) {
std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
@ -253,17 +252,18 @@ struct PerformReduction
log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type));
celldone.insert(drv.first);
}
int max_child_dept = 0;
int max_child_depth = 0;
for (auto &bit : drv.second)
max_child_dept = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_dept);
sigdepth[out] = max_child_dept + 1;
max_child_depth = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_depth);
sigdepth[out] = max_child_depth + 1;
} else {
pi_bits.push_back(out);
sat_pi.push_back(satgen.importSigSpec(out).front());
ez.assume(ez.NOT(satgen.importUndefSigSpec(out).front()));
sigdepth[out] = 0;
}
return sigdepth[out];
return sigdepth.at(out);
}
PerformReduction(SigMap &sigmap, drivers_t &drivers, std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs, std::vector<RTLIL::SigBit> &bits, int cone_size) :