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Merge pull request #1683 from whitequark/write_verilog-memattrs

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write_verilog: dump $mem cell attributes
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whitequark 2020-02-07 02:54:04 +00:00 committed by GitHub
parent 30854b9c7f e95a8ba763
commit 6f67dd8df5
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backends/verilog/verilog_backend.cc
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@ -1066,6 +1066,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// initial begin // initial begin
// memid[0] = ... // memid[0] = ...
// end // end
dump_attributes(f, indent.c_str(), cell->attributes);
f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset); f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset);
if (use_init) if (use_init)
{ {