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Merge pull request #3778 from jix/yw_clk2fflogic

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N. Engelhardt 2023-06-05 16:15:04 +02:00 • committed by GitHub
commit 6f5d984bdb
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7 changed files with 70 additions and 17 deletions
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backends/aiger/aiger.cc
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@ -736,6 +736,9 @@ struct AigerWriter
auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? ID::Y : ID::Q);
SigSpec sig = sigmap(sig_qy);
if (cell->get_bool_attribute(ID(clk2fflogic)))
sig_qy = cell->getPort(ID::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output
for (int i = 0; i < GetSize(sig_qy); i++) {
if (sig_qy[i].wire == nullptr || sig[i].wire == nullptr)
continue;