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Merge pull request #3778 from jix/yw_clk2fflogic

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N. Engelhardt 2023-06-05 16:15:04 +02:00 • committed by GitHub
commit 6f5d984bdb
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7 changed files with 70 additions and 17 deletions
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3
backends/aiger/aiger.cc
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@ -736,6 +736,9 @@ struct AigerWriter
auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? ID::Y : ID::Q);
SigSpec sig = sigmap(sig_qy);
if (cell->get_bool_attribute(ID(clk2fflogic)))
sig_qy = cell->getPort(ID::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output
for (int i = 0; i < GetSize(sig_qy); i++) {
if (sig_qy[i].wire == nullptr || sig[i].wire == nullptr)
continue;

5
backends/btor/btor.cc
View file

@ -728,7 +728,10 @@ struct BtorWorker
else
btorf("%d state %d %s\n", nid, sid, log_id(symbol));
ywmap_state(sig_q);
if (cell->get_bool_attribute(ID(clk2fflogic)))
ywmap_state(cell->getPort(ID::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
else
ywmap_state(sig_q);
if (nid_init_val >= 0) {
int nid_init = next_nid++;

3
backends/smt2/smt2.cc
View file

@ -626,8 +626,9 @@ struct Smt2Worker
}
bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst));
bool clk2fflogic = cell->type == ID($anyinit) && cell->get_bool_attribute(ID(clk2fflogic));
int smtoffset = 0;
for (auto chunk : cell->getPort(QY).chunks()) {
for (auto chunk : cell->getPort(clk2fflogic ? ID::D : QY).chunks()) {
if (chunk.is_wire())
decls.push_back(witness_signal(init_only ? "init" : "seq", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset));
smtoffset += chunk.width;