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aiger/xaiger: use odd for negedge clk, even for posedge

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Since abc9 doesn't like negative mergeability values
This commit is contained in:
Eddie Hung 2020-04-15 12:15:36 -07:00
parent fb447951be
commit 6f4f795953
2 changed files with 13 additions and 10 deletions
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16
backends/aiger/xaiger.cc
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@ -627,21 +627,25 @@ struct XAigerWriter
write_s_buffer(ff_bits.size()); write_s_buffer(ff_bits.size());
dict<SigBit, int> clk_to_mergeability; dict<SigBit, int> clk_to_mergeability;
for (const auto &i : ff_bits) {
const Cell *cell = i.second;
log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_)));
SigBit clock = sigmap(cell->getPort(ID::C));
clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size()*2+1));
}
for (const auto &i : ff_bits) { for (const auto &i : ff_bits) {
const SigBit &d = i.first; const SigBit &d = i.first;
const Cell *cell = i.second; const Cell *cell = i.second;
log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_)));
SigBit clock = sigmap(cell->getPort(ID::C)); SigBit clock = sigmap(cell->getPort(ID::C));
auto r = clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size() + 1)); int mergeability = clk_to_mergeability.at(clock);
int mergeability = r.first->second;
log_assert(mergeability > 0); log_assert(mergeability > 0);
if (cell->type == ID($_DFF_N_)) if (cell->type == ID($_DFF_N_))
write_r_buffer(-mergeability);
else if (cell->type == ID($_DFF_P_))
write_r_buffer(mergeability); write_r_buffer(mergeability);
else if (cell->type == ID($_DFF_P_))
write_r_buffer(mergeability+1);
else log_abort(); else log_abort();
SigBit Q = sigmap(cell->getPort(ID::Q)); SigBit Q = sigmap(cell->getPort(ID::Q));

7
frontends/aiger/aigerparse.cc
View file

@ -789,13 +789,12 @@ void AigerReader::post_process()
Cell* ff; Cell* ff;
int clock_index = mergeability[i]; int clock_index = mergeability[i];
if (clock_index < 0) { if (clock_index & 1) {
ff = module->addCell(NEW_ID, ID($_DFF_N_)); ff = module->addCell(NEW_ID, ID($_DFF_N_));
clock_index = -clock_index; clock_index--;
} }
else if (clock_index > 0) else
ff = module->addCell(NEW_ID, ID($_DFF_P_)); ff = module->addCell(NEW_ID, ID($_DFF_P_));
else log_abort();
auto r = mergeability_to_clock.insert(clock_index); auto r = mergeability_to_clock.insert(clock_index);
if (r.second) if (r.second)
r.first->second = module->addWire(NEW_ID); r.first->second = module->addWire(NEW_ID);