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aiger/xaiger: use odd for negedge clk, even for posedge

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Since abc9 doesn't like negative mergeability values
This commit is contained in:
Eddie Hung 2020-04-15 12:15:36 -07:00
parent fb447951be
commit 6f4f795953
2 changed files with 13 additions and 10 deletions
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7
frontends/aiger/aigerparse.cc
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@ -789,13 +789,12 @@ void AigerReader::post_process()
Cell* ff;
int clock_index = mergeability[i];
if (clock_index < 0) {
if (clock_index & 1) {
ff = module->addCell(NEW_ID, ID($_DFF_N_));
clock_index = -clock_index;
clock_index--;
}
else if (clock_index > 0)
else
ff = module->addCell(NEW_ID, ID($_DFF_P_));
else log_abort();
auto r = mergeability_to_clock.insert(clock_index);
if (r.second)
r.first->second = module->addWire(NEW_ID);