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Merge remote-tracking branch 'origin/master' into xaig

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Eddie Hung 2019-06-25 09:33:11 -07:00
commit 6f36ec8ecf
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techlibs/xilinx/cells_xtra.v
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@ -3694,13 +3694,6 @@ module RAM32M (...);
input WE;
endmodule
module RAM32X1D (...);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output DPO, SPO;
input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE;
endmodule
module RAM32X1S (...);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;