mirror of
https://github.com/YosysHQ/yosys
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rtlil_frontend, rtlil_backend: dump statics as strings, comments for src
This commit is contained in:
Emil J. Tywoniak
parent
9cb838febe
commit
6f1ca02a90
3 changed files with 252 additions and 161 deletions
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@ -32,18 +32,19 @@ USING_YOSYS_NAMESPACE
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using namespace RTLIL_BACKEND;
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YOSYS_NAMESPACE_BEGIN
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void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design, bool stringify)
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{
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// Emit the typed src field first. It is not stored in obj->attributes
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// — the dict no longer holds ID::src under any circumstance. Backends
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// that want to materialize the pipe-joined literal pass resolve_src.
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// that want to materialize the pipe-joined literal pass stringify.
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if (design && design->obj_src_id(obj) != Twine::Null) {
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TwineRef id = design->obj_src_id(obj);
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f << stringf("%s" "attribute \\src ", indent);
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if (resolve_src) {
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if (stringify) {
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dump_const(f, RTLIL::Const(design->twines.str(id)));
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} else {
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dump_const(f, RTLIL::Const(stringf("@%zu", id)));
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f << stringf(" # %s", design->twines.str(id).c_str());
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}
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f << stringf("\n");
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}
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@ -59,7 +60,11 @@ void RTLIL_BACKEND::dump_twines(std::ostream &f, const RTLIL::Design *design)
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if (!design || design->twines.size() == 0)
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return;
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f << stringf("twines\n");
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for (TwineRef id = 0; id < STATIC_TWINE_END; id++) {
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std::vector<TwineRef> ids;
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for (auto it = design->twines.backing.begin(); it != design->twines.backing.end(); ++it)
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ids.push_back(STATIC_TWINE_END + design->twines.backing.get_index(it));
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std::sort(ids.begin(), ids.end());
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for (TwineRef id : ids) {
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const Twine &n = design->twines[id];
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if (n.is_leaf()) {
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f << stringf(" leaf %zu ", id);
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@ -141,38 +146,60 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
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}
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}
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void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint)
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static std::string twine_handle(TwineRef ref)
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{
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return stringf("%s@%zu", twine_is_public(ref) ? "$pub" : "$priv", (size_t)twine_untag(ref));
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}
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static std::string twine_ref(const RTLIL::Design *design, TwineRef ref, bool stringify)
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{
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if (stringify || twine_untag(ref) < STATIC_TWINE_END)
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return design->twines.str(ref);
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return twine_handle(ref);
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}
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static std::string twine_cmt(const RTLIL::Design *design, TwineRef ref, bool stringify)
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{
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if (stringify || twine_untag(ref) < STATIC_TWINE_END)
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return "";
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return stringf(" # %s", design->twines.str(ref).c_str());
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}
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void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint, bool stringify)
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{
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if (chunk.wire == NULL) {
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dump_const(f, chunk.data, chunk.width, chunk.offset, autoint);
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} else {
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TwineRef wref = chunk.wire->name.ref();
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std::string name = (stringify || twine_untag(wref) < STATIC_TWINE_END)
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? chunk.wire->name.str() : twine_handle(wref);
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if (chunk.width == chunk.wire->width && chunk.offset == 0)
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f << stringf("%s", chunk.wire->name);
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f << name;
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else if (chunk.width == 1)
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f << stringf("%s [%d]", chunk.wire->name, chunk.offset);
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f << stringf("%s [%d]", name.c_str(), chunk.offset);
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else
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f << stringf("%s [%d:%d]", chunk.wire->name, chunk.offset+chunk.width-1, chunk.offset);
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f << stringf("%s [%d:%d]", name.c_str(), chunk.offset+chunk.width-1, chunk.offset);
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}
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}
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void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint)
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void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint, bool stringify)
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{
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if (sig.is_chunk()) {
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dump_sigchunk(f, sig.as_chunk(), autoint);
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dump_sigchunk(f, sig.as_chunk(), autoint, stringify);
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} else {
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f << stringf("{ ");
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auto chunks = sig.chunks();
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for (const auto& chunk : reversed(chunks)) {
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dump_sigchunk(f, chunk, false);
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dump_sigchunk(f, chunk, false, stringify);
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f << stringf(" ");
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}
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f << stringf("}");
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}
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}
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void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool stringify)
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{
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dump_attributes(f, indent, wire, design, resolve_src);
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dump_attributes(f, indent, wire, design, stringify);
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if (wire->driverCell_) {
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f << stringf("%s" "# driver %s %s\n", indent,
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wire->driverCell()->name, wire->driverPort());
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@ -192,12 +219,12 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
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f << stringf("inout %d ", wire->port_id);
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if (wire->is_signed)
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f << stringf("signed ");
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f << stringf("%s\n", wire->name);
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f << twine_ref(design, wire->name.ref(), stringify) << twine_cmt(design, wire->name.ref(), stringify) << "\n";
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}
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void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design, bool stringify)
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{
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dump_attributes(f, indent, memory, design, resolve_src);
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dump_attributes(f, indent, memory, design, stringify);
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f << stringf("%s" "memory ", indent);
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if (memory->width != 1)
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f << stringf("width %d ", memory->width);
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@ -205,13 +232,15 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL
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f << stringf("size %d ", memory->size);
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if (memory->start_offset != 0)
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f << stringf("offset %d ", memory->start_offset);
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f << stringf("%s\n", design->twines.str(memory->meta_->name).c_str());
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f << twine_ref(design, memory->meta_->name, stringify) << twine_cmt(design, memory->meta_->name, stringify) << "\n";
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}
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void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design, bool stringify)
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{
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dump_attributes(f, indent, cell, design, resolve_src);
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f << stringf("%s" "cell %s %s\n", indent, cell->type.str(), cell->name.str());
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dump_attributes(f, indent, cell, design, stringify);
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f << stringf("%s" "cell ", indent);
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f << twine_ref(design, cell->type.ref(), stringify) << " " << twine_ref(design, cell->name.ref(), stringify)
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<< twine_cmt(design, cell->type.ref(), stringify) << twine_cmt(design, cell->name.ref(), stringify) << "\n";
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for (const auto& [name, param] : reversed(cell->parameters)) {
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f << stringf("%s parameter%s%s%s %s ", indent,
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(param.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
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@ -222,53 +251,54 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
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f << stringf("\n");
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}
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for (const auto& [port, sig] : reversed(cell->connections_)) {
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f << stringf("%s connect %s ", indent, design->twines.unescaped_str(port));
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dump_sigspec(f, sig);
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f << stringf("\n");
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f << stringf("%s connect ", indent);
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f << twine_ref(design, port, stringify) << " ";
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dump_sigspec(f, sig, true, stringify);
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f << twine_cmt(design, port, stringify) << "\n";
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}
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f << stringf("%s" "end\n", indent);
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}
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void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design, bool stringify)
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{
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for (const auto& [lhs, rhs] : cs->actions) {
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f << stringf("%s" "assign ", indent);
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dump_sigspec(f, lhs);
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dump_sigspec(f, lhs, true, stringify);
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f << stringf(" ");
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dump_sigspec(f, rhs);
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dump_sigspec(f, rhs, true, stringify);
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f << stringf("\n");
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}
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for (const auto& sw : cs->switches)
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dump_proc_switch(f, indent, sw, design, resolve_src);
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dump_proc_switch(f, indent, sw, design, stringify);
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}
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void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design, bool stringify)
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{
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dump_attributes(f, indent, sw, design, resolve_src);
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dump_attributes(f, indent, sw, design, stringify);
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f << stringf("%s" "switch ", indent);
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dump_sigspec(f, sw->signal);
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dump_sigspec(f, sw->signal, true, stringify);
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f << stringf("\n");
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for (const auto case_ : sw->cases)
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{
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dump_attributes(f, indent, case_, design, resolve_src);
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dump_attributes(f, indent, case_, design, stringify);
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f << stringf("%s case ", indent);
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for (size_t i = 0; i < case_->compare.size(); i++) {
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if (i > 0)
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f << stringf(" , ");
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dump_sigspec(f, case_->compare[i]);
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dump_sigspec(f, case_->compare[i], true, stringify);
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}
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f << stringf("\n");
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dump_proc_case_body(f, indent + " ", case_, design, resolve_src);
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dump_proc_case_body(f, indent + " ", case_, design, stringify);
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}
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f << stringf("%s" "end\n", indent);
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}
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void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design, bool stringify)
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{
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f << stringf("%s" "sync ", indent);
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switch (sy->type) {
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@ -277,7 +307,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
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if (0) case RTLIL::STp: f << stringf("posedge ");
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if (0) case RTLIL::STn: f << stringf("negedge ");
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if (0) case RTLIL::STe: f << stringf("edge ");
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dump_sigspec(f, sy->signal);
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dump_sigspec(f, sy->signal, true, stringify);
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f << stringf("\n");
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break;
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case RTLIL::STa: f << stringf("always\n"); break;
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@ -287,55 +317,57 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
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for (const auto& [lhs, rhs] : sy->actions) {
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f << stringf("%s update ", indent);
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dump_sigspec(f, lhs);
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dump_sigspec(f, lhs, true, stringify);
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f << stringf(" ");
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dump_sigspec(f, rhs);
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dump_sigspec(f, rhs, true, stringify);
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f << stringf("\n");
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}
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for (auto &it: sy->mem_write_actions) {
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dump_attributes(f, indent, &it, design, resolve_src);
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dump_attributes(f, indent, &it, design, stringify);
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f << stringf("%s memwr %s ", indent, it.memid);
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dump_sigspec(f, it.address);
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dump_sigspec(f, it.address, true, stringify);
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f << stringf(" ");
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dump_sigspec(f, it.data);
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dump_sigspec(f, it.data, true, stringify);
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f << stringf(" ");
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dump_sigspec(f, it.enable);
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dump_sigspec(f, it.enable, true, stringify);
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f << stringf(" ");
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dump_const(f, it.priority_mask);
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f << stringf("\n");
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}
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}
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void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design, bool resolve_src)
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void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design, bool stringify)
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{
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dump_attributes(f, indent, proc, design, resolve_src);
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f << stringf("%s" "process %s\n", indent, design->twines.str(proc->meta_->name).c_str());
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dump_proc_case_body(f, indent + " ", &proc->root_case, design, resolve_src);
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dump_attributes(f, indent, proc, design, stringify);
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f << stringf("%s" "process ", indent);
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f << twine_ref(design, proc->meta_->name, stringify) << twine_cmt(design, proc->meta_->name, stringify) << "\n";
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dump_proc_case_body(f, indent + " ", &proc->root_case, design, stringify);
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for (auto* sync : proc->syncs)
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dump_proc_sync(f, indent + " ", sync, design, resolve_src);
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dump_proc_sync(f, indent + " ", sync, design, stringify);
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f << stringf("%s" "end\n", indent);
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}
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void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right, bool stringify)
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{
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f << stringf("%s" "connect ", indent);
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dump_sigspec(f, left);
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dump_sigspec(f, left, true, stringify);
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f << stringf(" ");
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dump_sigspec(f, right);
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dump_sigspec(f, right, true, stringify);
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f << stringf("\n");
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}
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void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool resolve_src)
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void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool stringify)
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{
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bool print_header = flag_m || module->is_selected_whole();
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bool print_body = !flag_n || !module->is_selected_whole();
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if (print_header)
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{
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dump_attributes(f, indent, module, design, resolve_src);
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dump_attributes(f, indent, module, design, stringify);
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f << stringf("%s" "module %s\n", indent, design->twines.str(module->meta_->name).c_str());
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f << stringf("%s" "module ", indent);
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f << twine_ref(design, module->meta_->name, stringify) << twine_cmt(design, module->meta_->name, stringify) << "\n";
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if (!module->avail_parameters.empty()) {
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if (only_selected)
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@ -359,28 +391,28 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
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if (!only_selected || design->selected(module, wire)) {
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if (only_selected)
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f << stringf("\n");
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dump_wire(f, indent + " ", wire, design, resolve_src);
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dump_wire(f, indent + " ", wire, design, stringify);
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}
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for (const auto& [_, mem] : reversed(module->memories))
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if (!only_selected || design->selected(module, mem)) {
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if (only_selected)
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f << stringf("\n");
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dump_memory(f, indent + " ", mem, design, resolve_src);
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dump_memory(f, indent + " ", mem, design, stringify);
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}
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for (const auto& [_, cell] : reversed(module->cells_))
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if (!only_selected || design->selected(module, cell)) {
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if (only_selected)
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f << stringf("\n");
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dump_cell(f, indent + " ", cell, design, resolve_src);
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dump_cell(f, indent + " ", cell, design, stringify);
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}
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for (const auto& [_, process] : reversed(module->processes))
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if (!only_selected || design->selected(module, process)) {
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if (only_selected)
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f << stringf("\n");
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dump_proc(f, indent + " ", process, design, resolve_src);
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dump_proc(f, indent + " ", process, design, stringify);
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}
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bool first_conn_line = true;
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@ -398,7 +430,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
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if (show_conn) {
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if (only_selected && first_conn_line)
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f << stringf("\n");
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dump_conn(f, indent + " ", lhs, rhs);
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dump_conn(f, indent + " ", lhs, rhs, stringify);
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first_conn_line = false;
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}
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}
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@ -408,7 +440,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
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f << stringf("%s" "end\n", indent);
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}
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void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool resolve_src)
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void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool stringify)
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{
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int init_autoidx = autoidx;
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@ -428,7 +460,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
|
|||
if (only_selected)
|
||||
f << stringf("\n");
|
||||
f << stringf("autoidx %d\n", autoidx);
|
||||
if (!resolve_src)
|
||||
if (!stringify)
|
||||
dump_twines(f, design);
|
||||
}
|
||||
|
||||
|
|
@ -436,7 +468,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
|
|||
if (!only_selected || design->selected_module(module->meta_->name)) {
|
||||
if (only_selected)
|
||||
f << stringf("\n");
|
||||
dump_module(f, "", module, design, only_selected, flag_m, flag_n, resolve_src);
|
||||
dump_module(f, "", module, design, only_selected, flag_m, flag_n, stringify);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -463,18 +495,16 @@ struct RTLILBackend : public Backend {
|
|||
log(" -sort\n");
|
||||
log(" sort design in-place (used to be default).\n");
|
||||
log("\n");
|
||||
log(" -resolve-src\n");
|
||||
log(" expand twine references in src attributes inline. Without\n");
|
||||
log(" this flag the design-level twine pool is emitted as a\n");
|
||||
log(" `twines` header block and cell src attributes keep their\n");
|
||||
log(" compact \"@N\" reference form.\n");
|
||||
log(" -readable\n");
|
||||
log(" lose information for more readable files.\n");
|
||||
log(" Breaks perfect replayability.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
bool selected = false;
|
||||
bool do_sort = false;
|
||||
bool resolve_src = false;
|
||||
bool stringify = false;
|
||||
|
||||
log_header(design, "Executing RTLIL backend.\n");
|
||||
|
||||
|
|
@ -489,8 +519,8 @@ struct RTLILBackend : public Backend {
|
|||
do_sort = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-resolve-src") {
|
||||
resolve_src = true;
|
||||
if (arg == "-readable") {
|
||||
stringify = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
|
@ -503,7 +533,7 @@ struct RTLILBackend : public Backend {
|
|||
design->sort();
|
||||
|
||||
*f << stringf("# Generated by %s\n", yosys_maybe_version());
|
||||
RTLIL_BACKEND::dump_design(*f, design, selected, true, false, resolve_src);
|
||||
RTLIL_BACKEND::dump_design(*f, design, selected, true, false, stringify);
|
||||
}
|
||||
} RTLILBackend;
|
||||
|
||||
|
|
@ -531,17 +561,15 @@ struct DumpPass : public Pass {
|
|||
log(" -a <filename>\n");
|
||||
log(" like -outfile but append instead of overwrite\n");
|
||||
log("\n");
|
||||
log(" -resolve-src\n");
|
||||
log(" expand twine references in src attributes inline. Without\n");
|
||||
log(" this flag the design-level twine pool is emitted as a\n");
|
||||
log(" `twines` header block and cell src attributes keep their\n");
|
||||
log(" compact \"@N\" reference form.\n");
|
||||
log(" -readable\n");
|
||||
log(" lose information for more readable files.\n");
|
||||
log(" Breaks perfect replayability.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
std::string filename;
|
||||
bool flag_m = false, flag_n = false, append = false, resolve_src = false;
|
||||
bool flag_m = false, flag_n = false, append = false, stringify = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
|
|
@ -565,8 +593,8 @@ struct DumpPass : public Pass {
|
|||
flag_n = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-resolve-src") {
|
||||
resolve_src = true;
|
||||
if (arg == "-readable") {
|
||||
stringify = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
|
@ -590,7 +618,7 @@ struct DumpPass : public Pass {
|
|||
f = &buf;
|
||||
}
|
||||
|
||||
RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, resolve_src);
|
||||
RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, stringify);
|
||||
|
||||
if (!empty) {
|
||||
delete f;
|
||||
|
|
|
|||
|
|
@ -31,30 +31,22 @@
|
|||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
namespace RTLIL_BACKEND {
|
||||
// If `design` is non-null AND `resolve_src` is true, the ID::src
|
||||
// attribute is expanded through design->twines so the emitted
|
||||
// value is the flat path:line.col string. Otherwise the stored value
|
||||
// is written verbatim — including any "@N" twine references, which
|
||||
// the matching `twines` header block emitted by dump_design lets the
|
||||
// parser reconstruct on load.
|
||||
void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
|
||||
// Emit the design-level twine pool as a top-level `twines` block.
|
||||
// Skipped if the pool is empty.
|
||||
void dump_twines(std::ostream &f, const RTLIL::Design *design);
|
||||
void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true);
|
||||
void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true);
|
||||
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true);
|
||||
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design = nullptr, bool resolve_src = false);
|
||||
void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right);
|
||||
void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool resolve_src = false);
|
||||
void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool resolve_src = false);
|
||||
void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true, bool stringify = true);
|
||||
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true, bool stringify = true);
|
||||
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
void dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design = nullptr, bool stringify = false);
|
||||
void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right, bool stringify = true);
|
||||
void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool stringify = false);
|
||||
void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool stringify = false);
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue