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Update abc attributes on FD*E_1

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Eddie Hung 2019-06-05 12:33:40 -07:00
parent 67f744d428
commit 6ed15b7890
1 changed files with 26 additions and 6 deletions
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28
techlibs/xilinx/cells_sim.v
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@ -283,28 +283,48 @@ module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input
`endif `endif
endmodule endmodule
module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R); (* abc_box_id = 6, abc_flop /*, lib_whitebox */ *)
module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q <= INIT;
`ifndef _ABC
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
`else
always @* if (R) Q <= 1'b0; else if (CE) Q <= D;
`endif
endmodule endmodule
module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S); (* abc_box_id = 7, abc_flop /*, lib_whitebox */ *)
module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q <= INIT;
`ifndef _ABC
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
`else
always @* if (S) Q <= 1'b1; else if (CE) Q <= D;
`endif
endmodule endmodule
module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR); (* abc_box_id = 8, abc_flop /*, lib_whitebox */ *)
module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q <= INIT;
`ifndef _ABC
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
`else
always @* if (CLR) Q <= 1'b0; else if (CE) Q <= D;
`endif
endmodule endmodule
module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); (* abc_box_id = 9, abc_flop /*, lib_whitebox */ *)
module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q <= INIT;
`ifndef _ABC
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
`else
always @* if (PRE) Q <= 1'b1; else if (CE) Q <= D;
`endif
endmodule endmodule
(* abc_box_id = 4 /*, lib_whitebox*/ *) (* abc_box_id = 4 /*, lib_whitebox*/ *)