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https://github.com/YosysHQ/yosys
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Merge pull request #209 from Silimate/opt_ffa_pt2
opt_first_fit_alloc updates + tests + some nice refactoring
This commit is contained in:
Akash Levy
GitHub
commit
6e80c5348d
9 changed files with 1758 additions and 148 deletions
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@ -857,3 +857,356 @@ design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# ============================================================================
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# Group I: exclusive saturating first-fit (no category / broadcast)
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# ============================================================================
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#
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# Plain taken[]/done[] scan without same-cat coalescing: each enabled lane
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# takes the next free slot until NB slots are exhausted. Later requesters get
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# rank 0 / not done. This is the qor_vmw_slot_lane shape.
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# I1: exclusive dsel-only, N=8 NB=4 (equiv + fires).
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log -header "I1: exclusive saturating allocator N=8 NB=4 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, W=2) (
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input logic mode,
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input logic [N-1:0] req,
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output logic [N*W-1:0] dsel_flat
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);
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logic [N-1:0] en = req & {N{mode}};
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# I2: exclusive with raw-input enable + sibling done bus, N=16 NB=4.
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log -header "I2: exclusive N=16 NB=4 raw-input en + done (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=16, NB=4, W=2) (
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input logic [N-1:0] lane_en,
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output logic [N*W-1:0] dsel_flat,
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output logic [N-1:0] done_o
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);
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (lane_en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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assign done_o = done;
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# I3: exclusive with non-power-of-two slot budget (NB=3, W=2) -- learn nb=3.
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log -header "I3: exclusive NB=3 (non-power-of-two) N=8 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=3, W=2) (
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input logic [N-1:0] lane_en,
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output logic [N*W-1:0] dsel_flat
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);
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (lane_en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# I4: exclusive last-fit near-miss (scan slots NB-1..0) -> no rewrite.
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log -header "I4: exclusive last-fit near-miss -> no rewrite"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, W=2) (
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input logic [N-1:0] lane_en,
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output logic [N*W-1:0] dsel_flat
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);
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (lane_en[i])
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for (int j=NB-1;j>=0;j--)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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opt_first_fit_alloc
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select -assert-count 0 w:*ffa_*
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design -reset
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log -pop
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# I5: exclusive MSB-first scan (lanes N-1..0), N=8 NB=4 (equiv).
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log -header "I5: exclusive MSB-first scan N=8 NB=4 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, W=2) (
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input logic [N-1:0] lane_en,
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output logic [N*W-1:0] dsel_flat
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);
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=N-1;i>=0;i--)
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if (lane_en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# I6: exclusive + identity gather of wide lane payloads into NB slots
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# (qor_vmw_slot_lane shape: slot_data[j] = data[leader at j]).
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# DW != N so per-lane data buses are not mistaken for width-N enables.
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log -header "I6: exclusive + identity gather N=8 NB=4 DW=16 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, W=2, DW=16) (
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input logic [N-1:0] lane_en,
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input logic [N*DW-1:0] data_flat,
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output logic [N*W-1:0] dsel_flat,
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output logic [NB*DW-1:0] slot_flat
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);
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logic [W-1:0] dsel [0:N-1];
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logic [DW-1:0] data [0:N-1];
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logic [DW-1:0] slot_data [0:NB-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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for (genvar g=0;g<N;g++) assign data[g] = data_flat[g*DW +: DW];
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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for (int j=0;j<NB;j++) slot_data[j] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (lane_en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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slot_data[j] = data[i];
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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for (genvar g=0;g<NB;g++) assign slot_flat[g*DW +: DW] = slot_data[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# I7: exclusive and2 enable (req = a & b), with sibling done — the
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# qor_vmw_slot_lane enable shape after opt folds the named `req` wire.
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# Equiv covers the and2 fingerprint path; I6 already covers identity gather.
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log -header "I7: exclusive and2 enable + done N=16 NB=4 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=16, NB=4, W=2) (
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input logic [N-1:0] a,
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input logic [N-1:0] b,
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output logic [N*W-1:0] dsel_flat,
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output logic [N-1:0] done_o
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);
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logic [N-1:0] en = a & b;
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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assign done_o = done;
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# I8: exclusive and2 enable without a global `opt` — launch flop stays a
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# plain $dff (sync reset) so leaf runs are data_q halves. Covers the pre-opt
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# and2 path; $aldff sequential handling is exercised by qor_vmw_slot_lane.
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log -header "I8: exclusive and2 enable pre-opt N=8 NB=4 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, W=2) (
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input logic clk,
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input logic [2*N-1:0] wdata,
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output logic [N*W-1:0] dsel_flat
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);
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logic [2*N-1:0] data_q;
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always_ff @(posedge clk)
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data_q <= wdata;
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wire [N-1:0] req = data_q[N-1:0] & data_q[2*N-1:N];
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0;
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done = '0;
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for (int i=0;i<N;i++)
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if (req[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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# Intentionally no `opt`.
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# I9: exclusive with NB > max_therm_nb (8) — forces the binary saturating
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# Hillis–Steele fallback (emit_scan_exclusive_bin / emit_sat_add) instead of
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# the thermometer scan used by I1–I8.
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log -header "I9: exclusive binary-scan fallback N=16 NB=12 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=16, NB=12, W=4) (
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input logic mode,
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input logic [N-1:0] req,
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output logic [N*W-1:0] dsel_flat
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);
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logic [N-1:0] en = req & {N{mode}};
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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